Lines Matching refs:cxl_p2n_reg_t

57 } cxl_p2n_reg_t;  typedef
151 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
152 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
154 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
155 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
156 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
157 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
159 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
161 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
162 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
163 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
165 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
166 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
167 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
168 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
169 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
170 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
172 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
173 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
175 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
816 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)  in _cxl_p2n_addr()
821 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)  in cxl_p2n_write()
827 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)  in cxl_p2n_read()