594 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
608 			rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_write_ppbuf()
627 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,  in rtsx_pci_set_pull_ctl()
783 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,  in rtsx_pci_switch_clock()
785 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,  in rtsx_pci_switch_clock()
787 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);  in rtsx_pci_switch_clock()
788 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,  in rtsx_pci_switch_clock()
790 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);  in rtsx_pci_switch_clock()
791 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);  in rtsx_pci_switch_clock()
793 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
795 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,  in rtsx_pci_switch_clock()
1254 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);  in rtsx_pci_init_hw()
1256 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);  in rtsx_pci_init_hw()
1258 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);  in rtsx_pci_init_hw()
1260 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);  in rtsx_pci_init_hw()
1262 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,  in rtsx_pci_init_hw()
1265 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,  in rtsx_pci_init_hw()
1268 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,  in rtsx_pci_init_hw()
1271 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,  in rtsx_pci_init_hw()
1274 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);  in rtsx_pci_init_hw()
1277 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);  in rtsx_pci_init_hw()
1279 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,  in rtsx_pci_init_hw()
1284 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);  in rtsx_pci_init_hw()
1289 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);  in rtsx_pci_init_hw()
1295 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);  in rtsx_pci_init_hw()