94 				 unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_timing()  argument
99 	if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&  in atmel_smc_cs_conf_set_timing()
100 	    shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&  in atmel_smc_cs_conf_set_timing()
101 	    shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&  in atmel_smc_cs_conf_set_timing()
102 	    shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&  in atmel_smc_cs_conf_set_timing()
103 	    shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)  in atmel_smc_cs_conf_set_timing()
113 	conf->timings &= ~GENMASK(shift + 3, shift);  in atmel_smc_cs_conf_set_timing()
114 	conf->timings |= val << shift;  in atmel_smc_cs_conf_set_timing()
136 				unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_setup()  argument
141 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&  in atmel_smc_cs_conf_set_setup()
142 	    shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)  in atmel_smc_cs_conf_set_setup()
152 	conf->setup &= ~GENMASK(shift + 7, shift);  in atmel_smc_cs_conf_set_setup()
153 	conf->setup |= val << shift;  in atmel_smc_cs_conf_set_setup()
175 				unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_pulse()  argument
180 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&  in atmel_smc_cs_conf_set_pulse()
181 	    shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)  in atmel_smc_cs_conf_set_pulse()
191 	conf->pulse &= ~GENMASK(shift + 7, shift);  in atmel_smc_cs_conf_set_pulse()
192 	conf->pulse |= val << shift;  in atmel_smc_cs_conf_set_pulse()
214 				unsigned int shift, unsigned int ncycles)  in atmel_smc_cs_conf_set_cycle()  argument
219 	if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)  in atmel_smc_cs_conf_set_cycle()
229 	conf->cycle &= ~GENMASK(shift + 15, shift);  in atmel_smc_cs_conf_set_cycle()
230 	conf->cycle |= val << shift;  in atmel_smc_cs_conf_set_cycle()