Lines Matching refs:r1
49 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
50 str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
52 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
53 str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
55 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
56 str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
58 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
59 str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
61 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
62 str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
64 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
65 str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
67 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
68 str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
70 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
71 str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
73 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
74 str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
76 ldr r1, [r0, #EMIF_COS_CONFIG]
77 str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
79 ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
80 str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
82 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
83 str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
85 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
86 str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
88 ldr r1, [r0, #EMIF_OCP_CONFIG]
89 str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
95 ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
96 str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
98 ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
99 str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
101 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
102 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
104 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
105 str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
107 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
108 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
110 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
111 str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
118 ldr r1, [r3, r5]
119 str r1, [r4, r5]
141 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
142 str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
143 str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
145 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
146 str r1, [r0, #EMIF_SDRAM_TIMING_1]
147 str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
149 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
150 str r1, [r0, #EMIF_SDRAM_TIMING_2]
151 str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
153 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
154 str r1, [r0, #EMIF_SDRAM_TIMING_3]
155 str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
157 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
158 str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
159 str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
161 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
162 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
164 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
165 str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
167 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
168 str r1, [r0, #EMIF_COS_CONFIG]
170 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
171 str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
173 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
174 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
176 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
177 str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
179 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
180 str r1, [r0, #EMIF_OCP_CONFIG]
186 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
187 str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
189 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
190 str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
192 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
193 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
195 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
196 str r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
198 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
199 str r1, [r0, #EMIF_DLL_CALIB_CTRL]
201 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
202 str r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
204 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
205 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
215 ldr r1, [r3, r5]
216 str r1, [r4, r5]
228 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
229 str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
232 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
233 and r2, r1, #SDRAM_TYPE_MASK
235 streq r1, [r0, #EMIF_SDRAM_CONFIG]
272 2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
273 tst r1, #RDWRLVLFULL_START
294 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
295 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
296 orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
297 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
322 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
323 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
324 orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
325 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
326 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
327 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
330 1: ldr r1, [r0, #EMIF_STATUS]
331 tst r1, #EMIF_STATUS_READY
351 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
352 bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
353 str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
356 1: ldr r1, [r0, #EMIF_STATUS]
357 tst r1, #EMIF_STATUS_READY