Lines Matching refs:timing
577 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
582 timing = &emc->timings[i]; in tegra_emc_find_timing()
587 if (!timing) { in tegra_emc_find_timing()
592 return timing; in tegra_emc_find_timing()
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
606 if (!timing) in tegra_emc_prepare_timing_change()
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
611 else if (timing->emc_mode_1 & 0x1) in tegra_emc_prepare_timing_change()
643 if (!(timing->emc_bgbias_ctl0 & in tegra_emc_prepare_timing_change()
663 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && in tegra_emc_prepare_timing_change()
669 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && in tegra_emc_prepare_timing_change()
688 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { in tegra_emc_prepare_timing_change()
690 writel(timing->emc_ctt_term_ctrl, in tegra_emc_prepare_timing_change()
696 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) in tegra_emc_prepare_timing_change()
697 writel(timing->emc_burst_data[i], in tegra_emc_prepare_timing_change()
700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
701 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
703 tegra_mc_write_emem_configuration(emc->mc, timing->rate); in tegra_emc_prepare_timing_change()
705 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; in tegra_emc_prepare_timing_change()
709 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) in tegra_emc_prepare_timing_change()
710 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, in tegra_emc_prepare_timing_change()
713 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) in tegra_emc_prepare_timing_change()
714 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, in tegra_emc_prepare_timing_change()
717 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { in tegra_emc_prepare_timing_change()
718 val = timing->emc_auto_cal_config; in tegra_emc_prepare_timing_change()
728 if (timing->emc_zcal_interval != 0 && in tegra_emc_prepare_timing_change()
732 val = (timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
738 val = timing->emc_mrs_wait_cnt in tegra_emc_prepare_timing_change()
746 val = timing->emc_cfg_2; in tegra_emc_prepare_timing_change()
752 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
775 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
776 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
777 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
778 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); in tegra_emc_prepare_timing_change()
780 if ((timing->emc_mode_reset != last->emc_mode_reset) || in tegra_emc_prepare_timing_change()
782 val = timing->emc_mode_reset; in tegra_emc_prepare_timing_change()
792 if (timing->emc_mode_2 != last->emc_mode_2) in tegra_emc_prepare_timing_change()
793 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); in tegra_emc_prepare_timing_change()
794 if (timing->emc_mode_1 != last->emc_mode_1) in tegra_emc_prepare_timing_change()
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
796 if (timing->emc_mode_4 != last->emc_mode_4) in tegra_emc_prepare_timing_change()
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
801 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { in tegra_emc_prepare_timing_change()
811 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) in tegra_emc_prepare_timing_change()
812 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_complete_timing_change() local
830 if (!timing) in tegra_emc_complete_timing_change()
837 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) in tegra_emc_complete_timing_change()
838 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
842 if (timing->emc_cfg & EMC_CFG_PWR_MASK) in tegra_emc_complete_timing_change()
843 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
846 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); in tegra_emc_complete_timing_change()
850 timing->emc_bgbias_ctl0 & in tegra_emc_complete_timing_change()
852 val = timing->emc_bgbias_ctl0; in tegra_emc_complete_timing_change()
859 timing->emc_bgbias_ctl0) { in tegra_emc_complete_timing_change()
860 writel(timing->emc_bgbias_ctl0, in tegra_emc_complete_timing_change()
864 writel(timing->emc_auto_cal_interval, in tegra_emc_complete_timing_change()
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
875 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
881 struct emc_timing *timing) in emc_read_current_timing() argument
886 timing->emc_burst_data[i] = in emc_read_current_timing()
889 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
891 timing->emc_auto_cal_interval = 0; in emc_read_current_timing()
892 timing->emc_zcal_cnt_long = 0; in emc_read_current_timing()
893 timing->emc_mode_1 = 0; in emc_read_current_timing()
894 timing->emc_mode_2 = 0; in emc_read_current_timing()
895 timing->emc_mode_4 = 0; in emc_read_current_timing()
896 timing->emc_mode_reset = 0; in emc_read_current_timing()
921 struct emc_timing *timing, in load_one_timing_from_dt() argument
934 timing->rate = value; in load_one_timing_from_dt()
937 timing->emc_burst_data, in load_one_timing_from_dt()
938 ARRAY_SIZE(timing->emc_burst_data)); in load_one_timing_from_dt()
947 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
996 struct emc_timing *timing; in tegra_emc_load_timings_from_dt() local
1000 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
1008 timing = &emc->timings[i++]; in tegra_emc_load_timings_from_dt()
1010 err = load_one_timing_from_dt(emc, timing, child); in tegra_emc_load_timings_from_dt()
1017 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()