Lines Matching refs:x
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
28 #define VEPU_REG_VP8_QUT_ZB_AC_Y2(x) (((x) & 0x1ff) << 9) argument
29 #define VEPU_REG_VP8_QUT_ZB_AC_Y1(x) (((x) & 0x1ff) << 0) argument
31 #define VEPU_REG_VP8_QUT_RND_DC_CHR(x) (((x) & 0xff) << 16) argument
32 #define VEPU_REG_VP8_QUT_RND_DC_Y2(x) (((x) & 0xff) << 8) argument
33 #define VEPU_REG_VP8_QUT_RND_DC_Y1(x) (((x) & 0xff) << 0) argument
35 #define VEPU_REG_VP8_QUT_RND_AC_CHR(x) (((x) & 0xff) << 16) argument
36 #define VEPU_REG_VP8_QUT_RND_AC_Y2(x) (((x) & 0xff) << 8) argument
37 #define VEPU_REG_VP8_QUT_RND_AC_Y1(x) (((x) & 0xff) << 0) argument
39 #define VEPU_REG_VP8_SEG_FILTER_LEVEL(x) (((x) & 0x3f) << 25) argument
40 #define VEPU_REG_VP8_DEQUT_DC_CHR(x) (((x) & 0xff) << 17) argument
41 #define VEPU_REG_VP8_DEQUT_DC_Y2(x) (((x) & 0x1ff) << 8) argument
42 #define VEPU_REG_VP8_DEQUT_DC_Y1(x) (((x) & 0xff) << 0) argument
44 #define VEPU_REG_VP8_DEQUT_AC_CHR(x) (((x) & 0x1ff) << 18) argument
45 #define VEPU_REG_VP8_DEQUT_AC_Y2(x) (((x) & 0x1ff) << 9) argument
46 #define VEPU_REG_VP8_DEQUT_AC_Y1(x) (((x) & 0x1ff) << 0) argument
49 #define VEPU_REG_VP8_INTRA_4X4_PENALTY_0(x) (((x) & 0xfff) << 0) argument
50 #define VEPU_REG_VP8_INTRA_4x4_PENALTY_1(x) (((x) & 0xfff) << 16) argument
52 #define VEPU_REG_VP8_INTRA_16X16_PENALTY_0(x) (((x) & 0xfff) << 0) argument
53 #define VEPU_REG_VP8_INTRA_16X16_PENALTY_1(x) (((x) & 0xfff) << 16) argument
55 #define VEPU_REG_VP8_LF_MODE_DELTA_BPRED(x) (((x) & 0x1f) << 24) argument
56 #define VEPU_REG_VP8_LF_REF_DELTA_INTRA_MB(x) (((x) & 0x7f) << 16) argument
57 #define VEPU_REG_VP8_INTER_TYPE_BIT_COST(x) (((x) & 0xfff) << 0) argument
59 #define VEPU_REG_VP8_COEF_DMV_PENALTY(x) (((x) & 0xfff) << 16) argument
60 #define VEPU_REG_VP8_REF_FRAME(x) (((x) & 0xfff) << 0) argument
62 #define VEPU_REG_VP8_LF_REF_DELTA_ALT_REF(x) (((x) & 0x7f) << 16) argument
63 #define VEPU_REG_VP8_LF_REF_DELTA_LAST_REF(x) (((x) & 0x7f) << 8) argument
64 #define VEPU_REG_VP8_LF_REF_DELTA_GOLDEN(x) (((x) & 0x7f) << 0) argument
66 #define VEPU_REG_VP8_LF_MODE_DELTA_SPLITMV(x) (((x) & 0x7f) << 16) argument
67 #define VEPU_REG_VP8_LF_MODE_DELTA_ZEROMV(x) (((x) & 0x7f) << 8) argument
68 #define VEPU_REG_VP8_LF_MODE_DELTA_NEWMV(x) (((x) & 0x7f) << 0) argument
74 #define VEPU_REG_INTRA_AREA_TOP(x) (((x) & 0xff) << 24) argument
75 #define VEPU_REG_INTRA_AREA_BOTTOM(x) (((x) & 0xff) << 16) argument
76 #define VEPU_REG_INTRA_AREA_LEFT(x) (((x) & 0xff) << 8) argument
77 #define VEPU_REG_INTRA_AREA_RIGHT(x) (((x) & 0xff) << 0) argument
79 #define VEPU_REG_CIR_INTRA_FIRST_MB(x) (((x) & 0xffff) << 16) argument
80 #define VEPU_REG_CIR_INTRA_INTERVAL(x) (((x) & 0xffff) << 0) argument
88 #define VEPU_REG_AXI_CTRL_READ_ID(x) (((x) & 0xff) << 24) argument
89 #define VEPU_REG_AXI_CTRL_WRITE_ID(x) (((x) & 0xff) << 16) argument
90 #define VEPU_REG_AXI_CTRL_BURST_LEN(x) (((x) & 0x3f) << 8) argument
91 #define VEPU_REG_AXI_CTRL_INCREMENT_MODE(x) (((x) & 0x01) << 2) argument
92 #define VEPU_REG_AXI_CTRL_BIRST_DISCARD(x) (((x) & 0x01) << 1) argument
95 #define VEPU_REG_ROI_QP_DELTA_1 (((x) & 0xf) << 12)
96 #define VEPU_REG_ROI_QP_DELTA_2 (((x) & 0xf) << 8)
97 #define VEPU_REG_MAD_QP_ADJUSTMENT (((x) & 0xf) << 0)
101 #define VEPU_REG_QP_SUM(x) (((x) & 0x001fffff) * 2) argument
104 #define VEPU_REG_DEBLOCKING_FILTER_MODE(x) (((x) & 0x3) << 24) argument
105 #define VEPU_REG_CABAC_INIT_IDC(x) (((x) & 0x3) << 21) argument
110 #define VEPU_REG_H264_SLICE_SIZE(x) (((x) & 0x7f) << 8) argument
112 #define VEPU_REG_STREAM_START_OFFSET(x) (((x) & 0x3f) << 16) argument
113 #define VEPU_REG_SKIP_MACROBLOCK_PENALTY(x) (((x) & 0xff) << 8) argument
114 #define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) (((x) & 0x3) << 4) argument
115 #define VEPU_REG_IN_IMG_CTRL_OVRFLB(x) (((x) & 0xf) << 0) argument
117 #define VEPU_REG_IN_IMG_CHROMA_OFFSET(x) (((x) & 0x7) << 20) argument
118 #define VEPU_REG_IN_IMG_LUMA_OFFSET(x) (((x) & 0x7) << 16) argument
119 #define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) (((x) & 0x3fff) << 0) argument
121 #define VEPU_REG_RLC_SUM_OUT(x) (((x) & 0x007fffff) * 4) argument
123 #define VEPU_REG_VP8_SPLIT_PENALTY_4X4 (((x) & 0x1ff) << 19)
127 #define VEPU_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff)) argument
128 #define VEPU_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16) argument
129 #define VEPU_REG_CHECKPOINT_RESULT(x) \ argument
130 ((((x) >> (16 - 16 * ((i) & 1))) & 0xffff) * 32)
132 #define VEPU_REG_VP8_SEG0_RND_AC_Y1(x) (((x) & 0xff) << 23) argument
133 #define VEPU_REG_VP8_SEG0_ZBIN_AC_Y1(x) (((x) & 0x1ff) << 14) argument
134 #define VEPU_REG_VP8_SEG0_QUT_AC_Y1(x) (((x) & 0x3fff) << 0) argument
136 #define VEPU_REG_VP8_SEG0_RND_DC_Y2(x) (((x) & 0xff) << 23) argument
137 #define VEPU_REG_VP8_SEG0_ZBIN_DC_Y2(x) (((x) & 0x1ff) << 14) argument
138 #define VEPU_REG_VP8_SEG0_QUT_DC_Y2(x) (((x) & 0x3fff) << 0) argument
140 #define VEPU_REG_VP8_SEG0_RND_AC_Y2(x) (((x) & 0xff) << 23) argument
141 #define VEPU_REG_VP8_SEG0_ZBIN_AC_Y2(x) (((x) & 0x1ff) << 14) argument
142 #define VEPU_REG_VP8_SEG0_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
144 #define VEPU_REG_VP8_SEG0_RND_DC_CHR(x) (((x) & 0xff) << 23) argument
145 #define VEPU_REG_VP8_SEG0_ZBIN_DC_CHR(x) (((x) & 0x1ff) << 14) argument
146 #define VEPU_REG_VP8_SEG0_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
148 #define VEPU_REG_VP8_SEG0_RND_AC_CHR(x) (((x) & 0xff) << 23) argument
149 #define VEPU_REG_VP8_SEG0_ZBIN_AC_CHR(x) (((x) & 0x1ff) << 14) argument
150 #define VEPU_REG_VP8_SEG0_QUT_AC_CHR(x) (((x) & 0x3fff) << 0) argument
152 #define VEPU_REG_VP8_MV_REF_IDX1(x) (((x) & 0x03) << 26) argument
153 #define VEPU_REG_VP8_SEG0_DQUT_DC_Y2(x) (((x) & 0x1ff) << 17) argument
154 #define VEPU_REG_VP8_SEG0_DQUT_AC_Y1(x) (((x) & 0x1ff) << 8) argument
155 #define VEPU_REG_VP8_SEG0_DQUT_DC_Y1(x) (((x) & 0xff) << 0) argument
157 #define VEPU_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff)) argument
158 #define VEPU_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16) argument
163 #define VEPU_REG_VP8_MV_REF_IDX2(x) (((x) & 0x03) << 26) argument
164 #define VEPU_REG_VP8_SEG0_DQUT_AC_CHR(x) (((x) & 0x1ff) << 17) argument
165 #define VEPU_REG_VP8_SEG0_DQUT_DC_CHR(x) (((x) & 0xff) << 9) argument
166 #define VEPU_REG_VP8_SEG0_DQUT_AC_Y2(x) (((x) & 0x1ff) << 0) argument
169 #define VEPU_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0) argument
170 #define VEPU_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4) argument
171 #define VEPU_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8) argument
172 #define VEPU_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12) argument
173 #define VEPU_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16) argument
174 #define VEPU_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20) argument
175 #define VEPU_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24) argument
177 #define VEPU_REG_VP8_ZERO_MV_PENALTY_FOR_REF2(x) (((x) & 0xff) << 24) argument
178 #define VEPU_REG_VP8_FILTER_SHARPNESS(x) (((x) & 0x07) << 21) argument
179 #define VEPU_REG_VP8_FILTER_LEVEL(x) (((x) & 0x3f) << 15) argument
180 #define VEPU_REG_VP8_DCT_PARTITION_CNT(x) (((x) & 0x03) << 13) argument
181 #define VEPU_REG_VP8_BOOL_ENC_VALUE_BITS(x) (((x) & 0x1f) << 8) argument
182 #define VEPU_REG_VP8_BOOL_ENC_RANGE(x) (((x) & 0xff) << 0) argument
184 #define VEPU_REG_MAD_THRESHOLD(x) (((x) & 0x3f) << 24) argument
185 #define VEPU_REG_COMPLETED_SLICES(x) (((x) & 0xff) << 16) argument
186 #define VEPU_REG_IN_IMG_CTRL_FMT(x) (((x) & 0xf) << 4) argument
187 #define VEPU_REG_IN_IMG_ROTATE_MODE(x) (((x) & 0x3) << 2) argument
190 #define VEPU_REG_INTRA16X16_MODE(x) (((x) & 0xffff) << 16) argument
191 #define VEPU_REG_INTER_MODE(x) (((x) & 0xffff) << 0) argument
193 #define VEPU_REG_PPS_INIT_QP(x) (((x) & 0x3f) << 26) argument
194 #define VEPU_REG_SLICE_FILTER_ALPHA(x) (((x) & 0xf) << 22) argument
195 #define VEPU_REG_SLICE_FILTER_BETA(x) (((x) & 0xf) << 18) argument
196 #define VEPU_REG_CHROMA_QP_OFFSET(x) (((x) & 0x1f) << 13) argument
198 #define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1) argument
206 #define VEPU_REG_ROI1_TOP_MB(x) (((x) & 0xff) << 24) argument
207 #define VEPU_REG_ROI1_BOTTOM_MB(x) (((x) & 0xff) << 16) argument
208 #define VEPU_REG_ROI1_LEFT_MB(x) (((x) & 0xff) << 8) argument
209 #define VEPU_REG_ROI1_RIGHT_MB(x) (((x) & 0xff) << 0) argument
211 #define VEPU_REG_ROI2_TOP_MB(x) (((x) & 0xff) << 24) argument
212 #define VEPU_REG_ROI2_BOTTOM_MB(x) (((x) & 0xff) << 16) argument
213 #define VEPU_REG_ROI2_LEFT_MB(x) (((x) & 0xff) << 8) argument
214 #define VEPU_REG_ROI2_RIGHT_MB(x) (((x) & 0xff) << 0) argument
218 #define VEPU_REG_STABLE_MIN_VALUE(x) (((x) & 0xffffff) << 8) argument
219 #define VEPU_REG_STABLE_MODE_SEL(x) (((x) & 0x3) << 6) argument
220 #define VEPU_REG_STABLE_HOR_GMV(x) (((x) & 0x3f) << 0) argument
222 #define VEPU_REG_RGB2YUV_CONVERSION_COEFB(x) (((x) & 0xffff) << 16) argument
223 #define VEPU_REG_RGB2YUV_CONVERSION_COEFA(x) (((x) & 0xffff) << 0) argument
225 #define VEPU_REG_RGB2YUV_CONVERSION_COEFE(x) (((x) & 0xffff) << 16) argument
226 #define VEPU_REG_RGB2YUV_CONVERSION_COEFC(x) (((x) & 0xffff) << 0) argument
228 #define VEPU_REG_RGB2YUV_CONVERSION_COEFF(x) (((x) & 0xffff) << 0) argument
230 #define VEPU_REG_RGB_MASK_B_MSB(x) (((x) & 0x1f) << 16) argument
231 #define VEPU_REG_RGB_MASK_G_MSB(x) (((x) & 0x1f) << 8) argument
232 #define VEPU_REG_RGB_MASK_R_MSB(x) (((x) & 0x1f) << 0) argument
234 #define VEPU_REG_1MV_PENALTY(x) (((x) & 0x3ff) << 21) argument
235 #define VEPU_REG_QMV_PENALTY(x) (((x) & 0x3ff) << 11) argument
236 #define VEPU_REG_4MV_PENALTY(x) (((x) & 0x3ff) << 1) argument
239 #define VEPU_REG_H264_LUMA_INIT_QP(x) (((x) & 0x3f) << 26) argument
240 #define VEPU_REG_H264_QP_MAX(x) (((x) & 0x3f) << 20) argument
241 #define VEPU_REG_H264_QP_MIN(x) (((x) & 0x3f) << 14) argument
242 #define VEPU_REG_H264_CHKPT_DISTANCE(x) (((x) & 0xfff) << 0) argument
244 #define VEPU_REG_VP8_SEG0_RND_DC_Y1(x) (((x) & 0xff) << 23) argument
245 #define VEPU_REG_VP8_SEG0_ZBIN_DC_Y1(x) (((x) & 0x1ff) << 14) argument
246 #define VEPU_REG_VP8_SEG0_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
248 #define VEPU_REG_ZERO_MV_FAVOR_D2(x) (((x) & 0xf) << 20) argument
249 #define VEPU_REG_PENALTY_4X4MV(x) (((x) & 0x1ff) << 11) argument
250 #define VEPU_REG_MVC_VIEW_ID(x) (((x) & 0x7) << 8) argument
252 #define VEPU_REG_MVC_PRIORITY_ID(x) (((x) & 0x7) << 4) argument
253 #define VEPU_REG_MVC_TEMPORAL_ID(x) (((x) & 0x7) << 1) argument
256 #define VEPU_REG_MB_HEIGHT(x) (((x) & 0x1ff) << 20) argument
257 #define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 8) argument
265 #define VEPU_REG_MB_CNT_OUT(x) (((x) & 0xffff) << 16) argument
266 #define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 0) argument
275 #define VEPU_REG_TEST_COUNTER(x) (((x) & 0xf) << 20) argument
278 #define VEPU_REG_TEST_LEN(x) (((x) & 0x3ffff) << 0) argument
280 #define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24) argument
281 #define VEPU_REG_INTRA_PRED_MODE(x) (((x) & 0xff) << 16) argument
282 #define VEPU_REG_FRAME_NUM(x) (((x) & 0xffff) << 0) argument
284 #define VEPU_REG_MV_PENALTY_16X8_8X16(x) (((x) & 0x3ff) << 20) argument
285 #define VEPU_REG_MV_PENALTY_8X8(x) (((x) & 0x3ff) << 10) argument
286 #define VEPU_REG_MV_PENALTY_8X4_4X8(x) (((x) & 0x3ff) << 0) argument
305 #define VEPU_REG_DMV_PENALTY_TABLE_BIT(x, i) ((x) << (i) * 8) argument
307 #define VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(x, i) ((x) << (i) * 8) argument
311 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID(x) (((x) & 0x1f) << 25) argument
312 #define VDPU_REG_REF_BUF_CTRL2_REFBU2_THR(x) (((x) & 0xfff) << 13) argument
319 #define VDPU_REG_CONFIG_DEC_LATENCY(x) (((x) & 0x3f) << 1) argument
320 #define VDPU_REG_CONFIG_TILED_MODE_MSB(x) BIT(0) argument
323 #define VDPU_REG_DEC_CTRL3_INIT_QP(x) (((x) & 0x3f) << 25) argument
325 #define VDPU_REG_DEC_CTRL3_STREAM_LEN(x) (((x) & 0xffffff) << 0) argument
327 #define VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD(x) (((x) & 0x3fff) << 17) argument
328 #define VDPU_REG_ERR_CONC_STARTMB_X(x) (((x) & 0x1ff) << 8) argument
329 #define VDPU_REG_ERR_CONC_STARTMB_Y(x) (((x) & 0xff) << 0) argument
331 #define VDPU_REG_DEC_CTRL0_DEC_MODE(x) (((x) & 0xf) << 0) argument
353 #define VDPU_REG_PARAL_BUS_E(x) BIT(21) argument
354 #define VDPU_REG_CONFIG_DEC_MAX_BURST(x) (((x) & 0x1f) << 16) argument
355 #define VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID(x) (((x) & 0xff) << 8) argument
356 #define VDPU_REG_CONFIG_DEC_AXI_RD_ID(x) (((x) & 0xff) << 0) argument
388 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0(x) (((x) & 0x3ff) << 22) argument
389 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1(x) (((x) & 0x3ff) << 12) argument
390 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2(x) (((x) & 0x3ff) << 2) argument
398 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F5(x) (((x) & 0x1f) << 25) argument
399 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F4(x) (((x) & 0x1f) << 20) argument
400 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) argument
401 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) argument
402 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) argument
403 #define VDPU_REG_FWD_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) argument
405 #define VDPU_REG_REF_PIC_REFER1_NBR(x) (((x) & 0xffff) << 16) argument
406 #define VDPU_REG_REF_PIC_REFER0_NBR(x) (((x) & 0xffff) << 0) argument
411 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F5(x) (((x) & 0x1f) << 25) argument
412 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F4(x) (((x) & 0x1f) << 20) argument
413 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F3(x) (((x) & 0x1f) << 15) argument
414 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2(x) (((x) & 0x1f) << 10) argument
415 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1(x) (((x) & 0x1f) << 5) argument
416 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0(x) (((x) & 0x1f) << 0) argument
418 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F11(x) (((x) & 0x1f) << 25) argument
419 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F10(x) (((x) & 0x1f) << 20) argument
420 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F9(x) (((x) & 0x1f) << 15) argument
421 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F8(x) (((x) & 0x1f) << 10) argument
422 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F7(x) (((x) & 0x1f) << 5) argument
423 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F6(x) (((x) & 0x1f) << 0) argument
425 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F15(x) (((x) & 0x1f) << 15) argument
426 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F14(x) (((x) & 0x1f) << 10) argument
427 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F13(x) (((x) & 0x1f) << 5) argument
428 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_F12(x) (((x) & 0x1f) << 0) argument
430 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B5(x) (((x) & 0x1f) << 25) argument
431 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B4(x) (((x) & 0x1f) << 20) argument
432 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B3(x) (((x) & 0x1f) << 15) argument
433 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2(x) (((x) & 0x1f) << 10) argument
434 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1(x) (((x) & 0x1f) << 5) argument
435 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0(x) (((x) & 0x1f) << 0) argument
437 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B11(x) (((x) & 0x1f) << 25) argument
438 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B10(x) (((x) & 0x1f) << 20) argument
439 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B9(x) (((x) & 0x1f) << 15) argument
440 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B8(x) (((x) & 0x1f) << 10) argument
441 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B7(x) (((x) & 0x1f) << 5) argument
442 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B6(x) (((x) & 0x1f) << 0) argument
444 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B15(x) (((x) & 0x1f) << 15) argument
445 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B14(x) (((x) & 0x1f) << 10) argument
446 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B13(x) (((x) & 0x1f) << 5) argument
447 #define VDPU_REG_BD_REF_PIC_BINIT_RLIST_B12(x) (((x) & 0x1f) << 0) argument
449 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3(x) (((x) & 0x1f) << 15) argument
450 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2(x) (((x) & 0x1f) << 10) argument
451 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1(x) (((x) & 0x1f) << 5) argument
452 #define VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0(x) (((x) & 0x1f) << 0) argument
456 #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2(x) (((x) & 0x1f) << 22) argument
457 #define VDPU_REG_DEC_CTRL2_CH_QP_OFFSET(x) (((x) & 0x1f) << 17) argument
458 #define VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 9) argument
459 #define VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 0) argument
461 #define VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(x) (((x) & 0x3) << 16) argument
462 #define VDPU_REG_DEC_CTRL1_REF_FRAMES(x) (((x) & 0x1f) << 0) argument
466 #define VDPU_REG_DEC_CTRL4_FRAMENUM_LEN(x) (((x) & 0x1f) << 16) argument
467 #define VDPU_REG_DEC_CTRL4_FRAMENUM(x) (((x) & 0xffff) << 0) argument
469 #define VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN(x) (((x) & 0x7ff) << 16) argument
470 #define VDPU_REG_DEC_CTRL5_IDR_PIC_ID(x) (((x) & 0xffff) << 0) argument
472 #define VDPU_REG_DEC_CTRL6_PPS_ID(x) (((x) & 0xff) << 24) argument
473 #define VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE(x) (((x) & 0x1f) << 19) argument
474 #define VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE(x) (((x) & 0x1f) << 14) argument
475 #define VDPU_REG_DEC_CTRL6_POC_LENGTH(x) (((x) & 0xff) << 0) argument
487 #define VDPU_REG_DEC_PIC_MB_WIDTH(x) (((x) & 0x1ff) << 23) argument
488 #define VDPU_REG_DEC_MB_WIDTH_OFF(x) (((x) & 0xf) << 19) argument
489 #define VDPU_REG_DEC_PIC_MB_HEIGHT_P(x) (((x) & 0xff) << 11) argument
490 #define VDPU_REG_DEC_MB_HEIGHT_OFF(x) (((x) & 0xf) << 7) argument
491 #define VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT(x) (((x) & 0x7) << 3) argument
492 #define VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT(x) (((x) & 0x7) << 0) argument
494 #define VDPU_REG_DEC_CTRL4_DCT1_START_BIT(x) (((x) & 0x3f) << 26) argument
495 #define VDPU_REG_DEC_CTRL4_DCT2_START_BIT(x) (((x) & 0x3f) << 20) argument
499 #define VDPU_REG_DEC_CTRL2_STRM_START_BIT(x) (((x) & 0x3f) << 26) argument
500 #define VDPU_REG_DEC_CTRL2_STRM1_START_BIT(x) (((x) & 0x3f) << 18) argument
501 #define VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE(x) (((x) & 0xff) << 8) argument
502 #define VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE(x) (((x) & 0xff) << 0) argument
504 #define VDPU_REG_DEC_CTRL6_COEFFS_PART_AM(x) (((x) & 0xf) << 24) argument
505 #define VDPU_REG_DEC_CTRL6_STREAM1_LEN(x) (((x) & 0xffffff) << 0) argument
507 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_1(x) (((x) & 0x3ff) << 22) argument
508 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_2(x) (((x) & 0x3ff) << 12) argument
509 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_3(x) (((x) & 0x3ff) << 2) argument
511 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_0(x) (((x) & 0x3ff) << 22) argument
512 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_1(x) (((x) & 0x3ff) << 12) argument
513 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_2(x) (((x) & 0x3ff) << 2) argument
515 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_6_3(x) (((x) & 0x3ff) << 22) argument
516 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_0(x) (((x) & 0x3ff) << 12) argument
517 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_1(x) (((x) & 0x3ff) << 2) argument
519 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_2(x) (((x) & 0x3ff) << 22) argument
520 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_7_3(x) (((x) & 0x3ff) << 12) argument
521 #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1(x) (((x) & 0x3) << 10) argument
522 #define VDPU_REG_BD_REF_PIC_PRED_TAP_2_4(x) (((x) & 0x3) << 8) argument
523 #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1(x) (((x) & 0x3) << 6) argument
524 #define VDPU_REG_BD_REF_PIC_PRED_TAP_4_4(x) (((x) & 0x3) << 4) argument
525 #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1(x) (((x) & 0x3) << 2) argument
526 #define VDPU_REG_BD_REF_PIC_PRED_TAP_6_4(x) (((x) & 0x3) << 0) argument
528 #define VDPU_REG_REF_PIC_LF_LEVEL_0(x) (((x) & 0x3f) << 18) argument
529 #define VDPU_REG_REF_PIC_LF_LEVEL_1(x) (((x) & 0x3f) << 12) argument
530 #define VDPU_REG_REF_PIC_LF_LEVEL_2(x) (((x) & 0x3f) << 6) argument
531 #define VDPU_REG_REF_PIC_LF_LEVEL_3(x) (((x) & 0x3f) << 0) argument
533 #define VDPU_REG_REF_PIC_QUANT_DELTA_0(x) (((x) & 0x1f) << 27) argument
534 #define VDPU_REG_REF_PIC_QUANT_DELTA_1(x) (((x) & 0x1f) << 22) argument
535 #define VDPU_REG_REF_PIC_QUANT_0(x) (((x) & 0x7ff) << 11) argument
536 #define VDPU_REG_REF_PIC_QUANT_1(x) (((x) & 0x7ff) << 0) argument
540 #define VDPU_REG_REF_PIC_FILT_SHARPNESS(x) (((x) & 0x7) << 28) argument
541 #define VDPU_REG_FILT_MB_ADJ_0(x) (((x) & 0x7f) << 21) argument
542 #define VDPU_REG_FILT_MB_ADJ_1(x) (((x) & 0x7f) << 14) argument
543 #define VDPU_REG_FILT_MB_ADJ_2(x) (((x) & 0x7f) << 7) argument
544 #define VDPU_REG_FILT_MB_ADJ_3(x) (((x) & 0x7f) << 0) argument
546 #define VDPU_REG_REF_PIC_ADJ_0(x) (((x) & 0x7f) << 21) argument
547 #define VDPU_REG_REF_PIC_ADJ_1(x) (((x) & 0x7f) << 14) argument
548 #define VDPU_REG_REF_PIC_ADJ_2(x) (((x) & 0x7f) << 7) argument
549 #define VDPU_REG_REF_PIC_ADJ_3(x) (((x) & 0x7f) << 0) argument
557 #define VDPU_REG_FWD_PIC1_SEGMENT_BASE(x) ((x) << 0) argument
561 #define VDPU_REG_DEC_CTRL7_DCT3_START_BIT(x) (((x) & 0x3f) << 24) argument
562 #define VDPU_REG_DEC_CTRL7_DCT4_START_BIT(x) (((x) & 0x3f) << 18) argument
563 #define VDPU_REG_DEC_CTRL7_DCT5_START_BIT(x) (((x) & 0x3f) << 12) argument
564 #define VDPU_REG_DEC_CTRL7_DCT6_START_BIT(x) (((x) & 0x3f) << 6) argument
565 #define VDPU_REG_DEC_CTRL7_DCT7_START_BIT(x) (((x) & 0x3f) << 0) argument
567 #define VDPU_REG_REF_PIC_QUANT_DELTA_2(x) (((x) & 0x1f) << 27) argument
568 #define VDPU_REG_REF_PIC_QUANT_DELTA_3(x) (((x) & 0x1f) << 22) argument
569 #define VDPU_REG_REF_PIC_QUANT_2(x) (((x) & 0x7ff) << 11) argument
570 #define VDPU_REG_REF_PIC_QUANT_3(x) (((x) & 0x7ff) << 0) argument
572 #define VDPU_REG_REF_PIC_QUANT_DELTA_4(x) (((x) & 0x1f) << 27) argument
573 #define VDPU_REG_REF_PIC_QUANT_4(x) (((x) & 0x7ff) << 11) argument
574 #define VDPU_REG_REF_PIC_QUANT_5(x) (((x) & 0x7ff) << 0) argument
576 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_0_3(x) (((x) & 0x3ff) << 22) argument
577 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_0(x) (((x) & 0x3ff) << 12) argument
578 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_1(x) (((x) & 0x3ff) << 2) argument
580 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_2(x) (((x) & 0x3ff) << 22) argument
581 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_1_3(x) (((x) & 0x3ff) << 12) argument
582 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_0(x) (((x) & 0x3ff) << 2) argument
584 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_1(x) (((x) & 0x3ff) << 22) argument
585 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_2(x) (((x) & 0x3ff) << 12) argument
586 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_2_3(x) (((x) & 0x3ff) << 2) argument
588 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_0(x) (((x) & 0x3ff) << 22) argument
589 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_1(x) (((x) & 0x3ff) << 12) argument
590 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_2(x) (((x) & 0x3ff) << 2) argument
592 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_3_3(x) (((x) & 0x3ff) << 22) argument
593 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_0(x) (((x) & 0x3ff) << 12) argument
594 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_1(x) (((x) & 0x3ff) << 2) argument
596 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_2(x) (((x) & 0x3ff) << 22) argument
597 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_4_3(x) (((x) & 0x3ff) << 12) argument
598 #define VDPU_REG_PRED_FLT_PRED_BC_TAP_5_0(x) (((x) & 0x3ff) << 2) argument