592 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in cp_write()  function
601 	return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);  in cp_write_clr_set()
960 	cp_write(sd, 0x8f, 0x00);  in configure_predefined_video_timings()
961 	cp_write(sd, 0x90, 0x00);  in configure_predefined_video_timings()
962 	cp_write(sd, 0xa2, 0x00);  in configure_predefined_video_timings()
963 	cp_write(sd, 0xa3, 0x00);  in configure_predefined_video_timings()
964 	cp_write(sd, 0xa4, 0x00);  in configure_predefined_video_timings()
965 	cp_write(sd, 0xa5, 0x00);  in configure_predefined_video_timings()
966 	cp_write(sd, 0xa6, 0x00);  in configure_predefined_video_timings()
967 	cp_write(sd, 0xa7, 0x00);  in configure_predefined_video_timings()
968 	cp_write(sd, 0xab, 0x00);  in configure_predefined_video_timings()
969 	cp_write(sd, 0xac, 0x00);  in configure_predefined_video_timings()
1027 		cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);  in configure_custom_video_timings()
1028 		cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |  in configure_custom_video_timings()
1030 		cp_write(sd, 0xa4, cp_start_eav & 0xff);  in configure_custom_video_timings()
1033 		cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);  in configure_custom_video_timings()
1034 		cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |  in configure_custom_video_timings()
1036 		cp_write(sd, 0xa7, cp_end_vbi & 0xff);  in configure_custom_video_timings()
1047 	cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);  in configure_custom_video_timings()
1048 	cp_write(sd, 0x90, ch1_fr_ll & 0xff);  in configure_custom_video_timings()
1049 	cp_write(sd, 0xab, (height >> 4) & 0xff);  in configure_custom_video_timings()
1050 	cp_write(sd, 0xac, (height & 0x0f) << 4);  in configure_custom_video_timings()
1218 		cp_write(sd, 0x3c, ctrl->val);  in adv76xx_s_ctrl()
1221 		cp_write(sd, 0x3a, ctrl->val);  in adv76xx_s_ctrl()
1224 		cp_write(sd, 0x3b, ctrl->val);  in adv76xx_s_ctrl()
1227 		cp_write(sd, 0x3d, ctrl->val);  in adv76xx_s_ctrl()
1248 		cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);  in adv76xx_s_ctrl()
1249 		cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);  in adv76xx_s_ctrl()
1250 		cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));  in adv76xx_s_ctrl()
1801 		cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */  in select_input()
1802 		cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */  in select_input()
1803 		cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */  in select_input()
2833 	cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */  in adv76xx_core_init()
2854 	cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */  in adv76xx_core_init()
2865 	cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */  in adv76xx_core_init()
2866 	cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */  in adv76xx_core_init()
2867 	cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -  in adv76xx_core_init()
2869 	cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -  in adv76xx_core_init()
2871 	cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution  in adv76xx_core_init()