1421 	int rc;  in drxdap_fasi_read_block()  local
1483 		rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,  in drxdap_fasi_read_block()
1485 		if (rc == 0)  in drxdap_fasi_read_block()
1486 			rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);  in drxdap_fasi_read_block()
1489 		rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,  in drxdap_fasi_read_block()
1495 	} while (datasize && rc == 0);  in drxdap_fasi_read_block()
1497 	return rc;  in drxdap_fasi_read_block()
1524 	int rc;  in drxdap_fasi_read_reg16()  local
1529 	rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);  in drxdap_fasi_read_reg16()
1531 	return rc;  in drxdap_fasi_read_reg16()
1557 	int rc;  in drxdap_fasi_read_reg32()  local
1562 	rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);  in drxdap_fasi_read_reg32()
1566 	return rc;  in drxdap_fasi_read_reg32()
1767 	int rc = -EIO;  in drxdap_fasi_read_modify_write_reg16()  local
1773 	rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);  in drxdap_fasi_read_modify_write_reg16()
1774 	if (rc == 0)  in drxdap_fasi_read_modify_write_reg16()
1775 		rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);  in drxdap_fasi_read_modify_write_reg16()
1778 	return rc;  in drxdap_fasi_read_modify_write_reg16()
1840 	int rc;  in drxj_dap_rm_write_reg16short()  local
1846 	rc = drxdap_fasi_write_reg16(dev_addr,  in drxj_dap_rm_write_reg16short()
1850 	if (rc == 0) {  in drxj_dap_rm_write_reg16short()
1852 		rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,  in drxj_dap_rm_write_reg16short()
1855 	if (rc == 0) {  in drxj_dap_rm_write_reg16short()
1857 		rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,  in drxj_dap_rm_write_reg16short()
1860 	if (rc == 0) {  in drxj_dap_rm_write_reg16short()
1862 		rc = drxdap_fasi_write_reg16(dev_addr,  in drxj_dap_rm_write_reg16short()
1867 	return rc;  in drxj_dap_rm_write_reg16short()
2108 	int rc;  in drxj_dap_atomic_read_write_block()  local
2145 	rc = hi_command(dev_addr, &hi_cmd, &dummy);  in drxj_dap_atomic_read_write_block()
2146 	if (rc != 0) {  in drxj_dap_atomic_read_write_block()
2147 		pr_err("error %d\n", rc);  in drxj_dap_atomic_read_write_block()
2154 			rc = drxj_dap_read_reg16(dev_addr,  in drxj_dap_atomic_read_write_block()
2157 			if (rc) {  in drxj_dap_atomic_read_write_block()
2158 				pr_err("error %d\n", rc);  in drxj_dap_atomic_read_write_block()
2169 	return rc;  in drxj_dap_atomic_read_write_block()
2185 	int rc;  in drxj_dap_atomic_read_reg32()  local
2191 	rc = drxj_dap_atomic_read_write_block(dev_addr, addr,  in drxj_dap_atomic_read_reg32()
2194 	if (rc < 0)  in drxj_dap_atomic_read_reg32()
2207 	return rc;  in drxj_dap_atomic_read_reg32()
2238 	int rc;  in hi_cfg_command()  local
2250 	rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);  in hi_cfg_command()
2251 	if (rc != 0) {  in hi_cfg_command()
2252 		pr_err("error %d\n", rc);  in hi_cfg_command()
2262 	return rc;  in hi_cfg_command()
2282 	int rc;  in hi_command()  local
2289 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);  in hi_command()
2290 		if (rc != 0) {  in hi_command()
2291 			pr_err("error %d\n", rc);  in hi_command()
2294 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);  in hi_command()
2295 		if (rc != 0) {  in hi_command()
2296 			pr_err("error %d\n", rc);  in hi_command()
2299 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);  in hi_command()
2300 		if (rc != 0) {  in hi_command()
2301 			pr_err("error %d\n", rc);  in hi_command()
2304 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);  in hi_command()
2305 		if (rc != 0) {  in hi_command()
2306 			pr_err("error %d\n", rc);  in hi_command()
2311 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);  in hi_command()
2312 		if (rc != 0) {  in hi_command()
2313 			pr_err("error %d\n", rc);  in hi_command()
2316 		rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);  in hi_command()
2317 		if (rc != 0) {  in hi_command()
2318 			pr_err("error %d\n", rc);  in hi_command()
2331 	rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);  in hi_command()
2332 	if (rc != 0) {  in hi_command()
2333 		pr_err("error %d\n", rc);  in hi_command()
2354 			rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);  in hi_command()
2355 			if (rc != 0) {  in hi_command()
2356 				pr_err("error %d\n", rc);  in hi_command()
2362 		rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);  in hi_command()
2363 		if (rc != 0) {  in hi_command()
2364 			pr_err("error %d\n", rc);  in hi_command()
2372 	return rc;  in hi_command()
2393 	int rc;  in init_hi()  local
2400 	rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);  in init_hi()
2401 	if (rc != 0) {  in init_hi()
2402 		pr_err("error %d\n", rc);  in init_hi()
2434 	rc = hi_cfg_command(demod);  in init_hi()
2435 	if (rc != 0) {  in init_hi()
2436 		pr_err("error %d\n", rc);  in init_hi()
2443 	return rc;  in init_hi()
2480 	int rc;  in get_device_capabilities()  local
2486 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in get_device_capabilities()
2487 	if (rc != 0) {  in get_device_capabilities()
2488 		pr_err("error %d\n", rc);  in get_device_capabilities()
2491 	rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);  in get_device_capabilities()
2492 	if (rc != 0) {  in get_device_capabilities()
2493 		pr_err("error %d\n", rc);  in get_device_capabilities()
2496 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);  in get_device_capabilities()
2497 	if (rc != 0) {  in get_device_capabilities()
2498 		pr_err("error %d\n", rc);  in get_device_capabilities()
2526 	rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);  in get_device_capabilities()
2527 	if (rc != 0) {  in get_device_capabilities()
2528 		pr_err("error %d\n", rc);  in get_device_capabilities()
2535 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in get_device_capabilities()
2536 		if (rc != 0) {  in get_device_capabilities()
2537 			pr_err("error %d\n", rc);  in get_device_capabilities()
2540 		rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);  in get_device_capabilities()
2541 		if (rc != 0) {  in get_device_capabilities()
2542 			pr_err("error %d\n", rc);  in get_device_capabilities()
2546 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);  in get_device_capabilities()
2547 		if (rc != 0) {  in get_device_capabilities()
2548 			pr_err("error %d\n", rc);  in get_device_capabilities()
2659 	return rc;  in get_device_capabilities()
2732 	int rc;  in ctrl_set_cfg_mpeg_output()  local
2768 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);  in ctrl_set_cfg_mpeg_output()
2769 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2770 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2775 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);  in ctrl_set_cfg_mpeg_output()
2776 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2777 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2780 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);  in ctrl_set_cfg_mpeg_output()
2781 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2782 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2785 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);  in ctrl_set_cfg_mpeg_output()
2786 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2787 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2790 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);  in ctrl_set_cfg_mpeg_output()
2791 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2792 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2795 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);  in ctrl_set_cfg_mpeg_output()
2796 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2797 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2800 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);  in ctrl_set_cfg_mpeg_output()
2801 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2802 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2806 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);  in ctrl_set_cfg_mpeg_output()
2807 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2808 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2812 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);  in ctrl_set_cfg_mpeg_output()
2813 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2814 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2845 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2846 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2847 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2850 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2851 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2852 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2855 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);  in ctrl_set_cfg_mpeg_output()
2856 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2857 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2860 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2861 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2862 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2865 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2866 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2867 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2871 				rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);  in ctrl_set_cfg_mpeg_output()
2872 				if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2873 					pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2877 				rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);  in ctrl_set_cfg_mpeg_output()
2878 				if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2879 					pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2883 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);  in ctrl_set_cfg_mpeg_output()
2884 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2885 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2888 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);  in ctrl_set_cfg_mpeg_output()
2889 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2890 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2899 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);  in ctrl_set_cfg_mpeg_output()
2900 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2901 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
2904 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);  in ctrl_set_cfg_mpeg_output()
2905 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
2906 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3061 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RAT…  in ctrl_set_cfg_mpeg_output()
3062 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3063 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3066 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RAT…  in ctrl_set_cfg_mpeg_output()
3067 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3068 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3071 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MO…  in ctrl_set_cfg_mpeg_output()
3072 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3073 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3076 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MO…  in ctrl_set_cfg_mpeg_output()
3077 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3078 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3081 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);  in ctrl_set_cfg_mpeg_output()
3082 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3083 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3088 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);  in ctrl_set_cfg_mpeg_output()
3089 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3090 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3095 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);  in ctrl_set_cfg_mpeg_output()
3096 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3097 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3100 			rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);  in ctrl_set_cfg_mpeg_output()
3101 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3102 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3107 		rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);  in ctrl_set_cfg_mpeg_output()
3108 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3109 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3114 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);  in ctrl_set_cfg_mpeg_output()
3115 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3116 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3119 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);  in ctrl_set_cfg_mpeg_output()
3120 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3121 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3124 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);  in ctrl_set_cfg_mpeg_output()
3125 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3126 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3132 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);  in ctrl_set_cfg_mpeg_output()
3133 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3134 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3138 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);  in ctrl_set_cfg_mpeg_output()
3139 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3140 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3143 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);  in ctrl_set_cfg_mpeg_output()
3144 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3145 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3148 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR…  in ctrl_set_cfg_mpeg_output()
3149 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3150 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3153 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);  in ctrl_set_cfg_mpeg_output()
3154 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3155 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3161 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3162 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3163 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3171 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3172 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3173 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3176 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3177 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3178 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3181 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3182 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3183 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3186 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3187 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3188 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3191 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3192 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3193 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3196 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3197 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3198 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3201 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3202 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3203 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3206 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);  in ctrl_set_cfg_mpeg_output()
3207 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3208 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3212 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3213 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3214 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3217 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3218 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3219 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3222 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3223 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3224 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3227 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3228 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3229 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3232 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3233 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3234 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3237 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3238 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3239 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3242 			rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3243 			if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3244 				pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3249 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3250 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3251 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3255 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3256 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3257 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3262 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);  in ctrl_set_cfg_mpeg_output()
3263 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3264 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3268 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3269 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3270 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3273 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3274 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3275 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3278 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3279 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3280 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3283 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3284 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3285 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3288 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3289 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3290 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3293 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3294 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3295 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3298 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3299 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3300 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3303 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3304 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3305 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3308 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3309 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3310 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3313 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3314 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3315 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3318 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3319 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3320 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3323 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3324 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3325 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3329 		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3330 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3331 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3335 		rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_cfg_mpeg_output()
3336 		if (rc != 0) {  in ctrl_set_cfg_mpeg_output()
3337 			pr_err("error %d\n", rc);  in ctrl_set_cfg_mpeg_output()
3347 	return rc;  in ctrl_set_cfg_mpeg_output()
3374 	int rc;  in set_mpegtei_handling()  local
3382 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);  in set_mpegtei_handling()
3383 	if (rc != 0) {  in set_mpegtei_handling()
3384 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3387 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);  in set_mpegtei_handling()
3388 	if (rc != 0) {  in set_mpegtei_handling()
3389 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3392 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);  in set_mpegtei_handling()
3393 	if (rc != 0) {  in set_mpegtei_handling()
3394 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3412 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);  in set_mpegtei_handling()
3413 	if (rc != 0) {  in set_mpegtei_handling()
3414 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3417 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);  in set_mpegtei_handling()
3418 	if (rc != 0) {  in set_mpegtei_handling()
3419 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3422 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);  in set_mpegtei_handling()
3423 	if (rc != 0) {  in set_mpegtei_handling()
3424 		pr_err("error %d\n", rc);  in set_mpegtei_handling()
3430 	return rc;  in set_mpegtei_handling()
3447 	int rc;  in bit_reverse_mpeg_output()  local
3453 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);  in bit_reverse_mpeg_output()
3454 	if (rc != 0) {  in bit_reverse_mpeg_output()
3455 		pr_err("error %d\n", rc);  in bit_reverse_mpeg_output()
3465 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);  in bit_reverse_mpeg_output()
3466 	if (rc != 0) {  in bit_reverse_mpeg_output()
3467 		pr_err("error %d\n", rc);  in bit_reverse_mpeg_output()
3473 	return rc;  in bit_reverse_mpeg_output()
3491 	int rc;  in set_mpeg_start_width()  local
3500 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);  in set_mpeg_start_width()
3501 		if (rc != 0) {  in set_mpeg_start_width()
3502 			pr_err("error %d\n", rc);  in set_mpeg_start_width()
3508 		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);  in set_mpeg_start_width()
3509 		if (rc != 0) {  in set_mpeg_start_width()
3510 			pr_err("error %d\n", rc);  in set_mpeg_start_width()
3517 	return rc;  in set_mpeg_start_width()
3537 	int rc;  in ctrl_set_uio_cfg()  local
3545 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in ctrl_set_uio_cfg()
3546 	if (rc != 0) {  in ctrl_set_uio_cfg()
3547 		pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3565 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3566 			if (rc != 0) {  in ctrl_set_uio_cfg()
3567 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3588 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3589 			if (rc != 0) {  in ctrl_set_uio_cfg()
3590 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3611 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3612 			if (rc != 0) {  in ctrl_set_uio_cfg()
3613 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3632 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);  in ctrl_set_uio_cfg()
3633 			if (rc != 0) {  in ctrl_set_uio_cfg()
3634 				pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3650 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_uio_cfg()
3651 	if (rc != 0) {  in ctrl_set_uio_cfg()
3652 		pr_err("error %d\n", rc);  in ctrl_set_uio_cfg()
3658 	return rc;  in ctrl_set_uio_cfg()
3672 	int rc;  in ctrl_uio_write()  local
3682 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in ctrl_uio_write()
3683 	if (rc != 0) {  in ctrl_uio_write()
3684 		pr_err("error %d\n", rc);  in ctrl_uio_write()
3704 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3705 		if (rc != 0) {  in ctrl_uio_write()
3706 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3711 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);  in ctrl_uio_write()
3712 		if (rc != 0) {  in ctrl_uio_write()
3713 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3722 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);  in ctrl_uio_write()
3723 		if (rc != 0) {  in ctrl_uio_write()
3724 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3743 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3744 		if (rc != 0) {  in ctrl_uio_write()
3745 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3750 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);  in ctrl_uio_write()
3751 		if (rc != 0) {  in ctrl_uio_write()
3752 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3761 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);  in ctrl_uio_write()
3762 		if (rc != 0) {  in ctrl_uio_write()
3763 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3782 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3783 		if (rc != 0) {  in ctrl_uio_write()
3784 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3789 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);  in ctrl_uio_write()
3790 		if (rc != 0) {  in ctrl_uio_write()
3791 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3800 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);  in ctrl_uio_write()
3801 		if (rc != 0) {  in ctrl_uio_write()
3802 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3822 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);  in ctrl_uio_write()
3823 		if (rc != 0) {  in ctrl_uio_write()
3824 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3829 		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);  in ctrl_uio_write()
3830 		if (rc != 0) {  in ctrl_uio_write()
3831 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3840 		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);  in ctrl_uio_write()
3841 		if (rc != 0) {  in ctrl_uio_write()
3842 			pr_err("error %d\n", rc);  in ctrl_uio_write()
3852 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_uio_write()
3853 	if (rc != 0) {  in ctrl_uio_write()
3854 		pr_err("error %d\n", rc);  in ctrl_uio_write()
3860 	return rc;  in ctrl_uio_write()
3917 	int rc;  in smart_ant_init()  local
3924 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);  in smart_ant_init()
3925 	if (rc != 0) {  in smart_ant_init()
3926 		pr_err("error %d\n", rc);  in smart_ant_init()
3930 	rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);  in smart_ant_init()
3931 	if (rc != 0) {  in smart_ant_init()
3932 		pr_err("error %d\n", rc);  in smart_ant_init()
3936 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) …  in smart_ant_init()
3937 		if (rc != 0) {  in smart_ant_init()
3938 			pr_err("error %d\n", rc);  in smart_ant_init()
3942 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M…  in smart_ant_init()
3943 		if (rc != 0) {  in smart_ant_init()
3944 			pr_err("error %d\n", rc);  in smart_ant_init()
3950 	rc = ctrl_set_uio_cfg(demod, &uio_cfg);  in smart_ant_init()
3951 	if (rc != 0) {  in smart_ant_init()
3952 		pr_err("error %d\n", rc);  in smart_ant_init()
3955 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);  in smart_ant_init()
3956 	if (rc != 0) {  in smart_ant_init()
3957 		pr_err("error %d\n", rc);  in smart_ant_init()
3960 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);  in smart_ant_init()
3961 	if (rc != 0) {  in smart_ant_init()
3962 		pr_err("error %d\n", rc);  in smart_ant_init()
3967 	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in smart_ant_init()
3968 	if (rc != 0) {  in smart_ant_init()
3969 		pr_err("error %d\n", rc);  in smart_ant_init()
3975 	return rc;  in smart_ant_init()
3980 	int rc;  in scu_command()  local
3989 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);  in scu_command()
3990 	if (rc != 0) {  in scu_command()
3991 		pr_err("error %d\n", rc);  in scu_command()
3999 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);  in scu_command()
4000 		if (rc != 0) {  in scu_command()
4001 			pr_err("error %d\n", rc);  in scu_command()
4006 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);  in scu_command()
4007 		if (rc != 0) {  in scu_command()
4008 			pr_err("error %d\n", rc);  in scu_command()
4013 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);  in scu_command()
4014 		if (rc != 0) {  in scu_command()
4015 			pr_err("error %d\n", rc);  in scu_command()
4020 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);  in scu_command()
4021 		if (rc != 0) {  in scu_command()
4022 			pr_err("error %d\n", rc);  in scu_command()
4027 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);  in scu_command()
4028 		if (rc != 0) {  in scu_command()
4029 			pr_err("error %d\n", rc);  in scu_command()
4040 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);  in scu_command()
4041 	if (rc != 0) {  in scu_command()
4042 		pr_err("error %d\n", rc);  in scu_command()
4049 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);  in scu_command()
4050 		if (rc != 0) {  in scu_command()
4051 			pr_err("error %d\n", rc);  in scu_command()
4068 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);  in scu_command()
4069 			if (rc != 0) {  in scu_command()
4070 				pr_err("error %d\n", rc);  in scu_command()
4075 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);  in scu_command()
4076 			if (rc != 0) {  in scu_command()
4077 				pr_err("error %d\n", rc);  in scu_command()
4082 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);  in scu_command()
4083 			if (rc != 0) {  in scu_command()
4084 				pr_err("error %d\n", rc);  in scu_command()
4089 			rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);  in scu_command()
4090 			if (rc != 0) {  in scu_command()
4091 				pr_err("error %d\n", rc);  in scu_command()
4124 	return rc;  in scu_command()
4145 	int rc;  in drxj_dap_scu_atomic_read_write_block()  local
4175 	rc = scu_command(dev_addr, &scu_cmd);  in drxj_dap_scu_atomic_read_write_block()
4176 	if (rc != 0) {  in drxj_dap_scu_atomic_read_write_block()
4177 		pr_err("error %d\n", rc);  in drxj_dap_scu_atomic_read_write_block()
4193 	return rc;  in drxj_dap_scu_atomic_read_write_block()
4209 	int rc;  in drxj_dap_scu_atomic_read_reg16()  local
4215 	rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);  in drxj_dap_scu_atomic_read_reg16()
4216 	if (rc < 0)  in drxj_dap_scu_atomic_read_reg16()
4217 		return rc;  in drxj_dap_scu_atomic_read_reg16()
4223 	return rc;  in drxj_dap_scu_atomic_read_reg16()
4237 	int rc;  in drxj_dap_scu_atomic_write_reg16()  local
4242 	rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);  in drxj_dap_scu_atomic_write_reg16()
4244 	return rc;  in drxj_dap_scu_atomic_write_reg16()
4260 	int rc;  in adc_sync_measurement()  local
4266 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);  in adc_sync_measurement()
4267 	if (rc != 0) {  in adc_sync_measurement()
4268 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4271 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);  in adc_sync_measurement()
4272 	if (rc != 0) {  in adc_sync_measurement()
4273 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4281 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);  in adc_sync_measurement()
4282 	if (rc != 0) {  in adc_sync_measurement()
4283 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4288 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);  in adc_sync_measurement()
4289 	if (rc != 0) {  in adc_sync_measurement()
4290 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4295 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);  in adc_sync_measurement()
4296 	if (rc != 0) {  in adc_sync_measurement()
4297 		pr_err("error %d\n", rc);  in adc_sync_measurement()
4305 	return rc;  in adc_sync_measurement()
4323 	int rc;  in adc_synchronization()  local
4328 	rc = adc_sync_measurement(demod, &count);  in adc_synchronization()
4329 	if (rc != 0) {  in adc_synchronization()
4330 		pr_err("error %d\n", rc);  in adc_synchronization()
4338 		rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);  in adc_synchronization()
4339 		if (rc != 0) {  in adc_synchronization()
4340 			pr_err("error %d\n", rc);  in adc_synchronization()
4345 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);  in adc_synchronization()
4346 		if (rc != 0) {  in adc_synchronization()
4347 			pr_err("error %d\n", rc);  in adc_synchronization()
4351 		rc = adc_sync_measurement(demod, &count);  in adc_synchronization()
4352 		if (rc != 0) {  in adc_synchronization()
4353 			pr_err("error %d\n", rc);  in adc_synchronization()
4364 	return rc;  in adc_synchronization()
4390 	int rc;  in init_agc()  local
4424 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);  in init_agc()
4425 		if (rc != 0) {  in init_agc()
4426 			pr_err("error %d\n", rc);  in init_agc()
4429 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);  in init_agc()
4430 		if (rc != 0) {  in init_agc()
4431 			pr_err("error %d\n", rc);  in init_agc()
4434 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);  in init_agc()
4435 		if (rc != 0) {  in init_agc()
4436 			pr_err("error %d\n", rc);  in init_agc()
4439 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);  in init_agc()
4440 		if (rc != 0) {  in init_agc()
4441 			pr_err("error %d\n", rc);  in init_agc()
4444 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);  in init_agc()
4445 		if (rc != 0) {  in init_agc()
4446 			pr_err("error %d\n", rc);  in init_agc()
4449 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);  in init_agc()
4450 		if (rc != 0) {  in init_agc()
4451 			pr_err("error %d\n", rc);  in init_agc()
4454 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);  in init_agc()
4455 		if (rc != 0) {  in init_agc()
4456 			pr_err("error %d\n", rc);  in init_agc()
4459 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);  in init_agc()
4460 		if (rc != 0) {  in init_agc()
4461 			pr_err("error %d\n", rc);  in init_agc()
4464 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);  in init_agc()
4465 		if (rc != 0) {  in init_agc()
4466 			pr_err("error %d\n", rc);  in init_agc()
4469 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);  in init_agc()
4470 		if (rc != 0) {  in init_agc()
4471 			pr_err("error %d\n", rc);  in init_agc()
4474 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);  in init_agc()
4475 		if (rc != 0) {  in init_agc()
4476 			pr_err("error %d\n", rc);  in init_agc()
4479 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);  in init_agc()
4480 		if (rc != 0) {  in init_agc()
4481 			pr_err("error %d\n", rc);  in init_agc()
4484 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);  in init_agc()
4485 		if (rc != 0) {  in init_agc()
4486 			pr_err("error %d\n", rc);  in init_agc()
4507 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);  in init_agc()
4508 		if (rc != 0) {  in init_agc()
4509 			pr_err("error %d\n", rc);  in init_agc()
4512 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);  in init_agc()
4513 		if (rc != 0) {  in init_agc()
4514 			pr_err("error %d\n", rc);  in init_agc()
4517 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);  in init_agc()
4518 		if (rc != 0) {  in init_agc()
4519 			pr_err("error %d\n", rc);  in init_agc()
4522 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);  in init_agc()
4523 		if (rc != 0) {  in init_agc()
4524 			pr_err("error %d\n", rc);  in init_agc()
4527 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);  in init_agc()
4528 		if (rc != 0) {  in init_agc()
4529 			pr_err("error %d\n", rc);  in init_agc()
4532 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);  in init_agc()
4533 		if (rc != 0) {  in init_agc()
4534 			pr_err("error %d\n", rc);  in init_agc()
4537 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);  in init_agc()
4538 		if (rc != 0) {  in init_agc()
4539 			pr_err("error %d\n", rc);  in init_agc()
4542 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);  in init_agc()
4543 		if (rc != 0) {  in init_agc()
4544 			pr_err("error %d\n", rc);  in init_agc()
4547 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);  in init_agc()
4548 		if (rc != 0) {  in init_agc()
4549 			pr_err("error %d\n", rc);  in init_agc()
4552 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);  in init_agc()
4553 		if (rc != 0) {  in init_agc()
4554 			pr_err("error %d\n", rc);  in init_agc()
4559 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);  in init_agc()
4560 		if (rc != 0) {  in init_agc()
4561 			pr_err("error %d\n", rc);  in init_agc()
4565 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);  in init_agc()
4566 		if (rc != 0) {  in init_agc()
4567 			pr_err("error %d\n", rc);  in init_agc()
4571 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);  in init_agc()
4572 		if (rc != 0) {  in init_agc()
4573 			pr_err("error %d\n", rc);  in init_agc()
4583 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);  in init_agc()
4584 	if (rc != 0) {  in init_agc()
4585 		pr_err("error %d\n", rc);  in init_agc()
4588 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);  in init_agc()
4589 	if (rc != 0) {  in init_agc()
4590 		pr_err("error %d\n", rc);  in init_agc()
4593 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);  in init_agc()
4594 	if (rc != 0) {  in init_agc()
4595 		pr_err("error %d\n", rc);  in init_agc()
4598 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);  in init_agc()
4599 	if (rc != 0) {  in init_agc()
4600 		pr_err("error %d\n", rc);  in init_agc()
4603 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);  in init_agc()
4604 	if (rc != 0) {  in init_agc()
4605 		pr_err("error %d\n", rc);  in init_agc()
4608 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);  in init_agc()
4609 	if (rc != 0) {  in init_agc()
4610 		pr_err("error %d\n", rc);  in init_agc()
4613 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);  in init_agc()
4614 	if (rc != 0) {  in init_agc()
4615 		pr_err("error %d\n", rc);  in init_agc()
4618 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);  in init_agc()
4619 	if (rc != 0) {  in init_agc()
4620 		pr_err("error %d\n", rc);  in init_agc()
4623 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);  in init_agc()
4624 	if (rc != 0) {  in init_agc()
4625 		pr_err("error %d\n", rc);  in init_agc()
4628 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);  in init_agc()
4629 	if (rc != 0) {  in init_agc()
4630 		pr_err("error %d\n", rc);  in init_agc()
4633 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);  in init_agc()
4634 	if (rc != 0) {  in init_agc()
4635 		pr_err("error %d\n", rc);  in init_agc()
4638 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);  in init_agc()
4639 	if (rc != 0) {  in init_agc()
4640 		pr_err("error %d\n", rc);  in init_agc()
4643 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);  in init_agc()
4644 	if (rc != 0) {  in init_agc()
4645 		pr_err("error %d\n", rc);  in init_agc()
4648 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);  in init_agc()
4649 	if (rc != 0) {  in init_agc()
4650 		pr_err("error %d\n", rc);  in init_agc()
4653 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);  in init_agc()
4654 	if (rc != 0) {  in init_agc()
4655 		pr_err("error %d\n", rc);  in init_agc()
4658 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);  in init_agc()
4659 	if (rc != 0) {  in init_agc()
4660 		pr_err("error %d\n", rc);  in init_agc()
4663 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);  in init_agc()
4664 	if (rc != 0) {  in init_agc()
4665 		pr_err("error %d\n", rc);  in init_agc()
4668 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);  in init_agc()
4669 	if (rc != 0) {  in init_agc()
4670 		pr_err("error %d\n", rc);  in init_agc()
4673 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);  in init_agc()
4674 	if (rc != 0) {  in init_agc()
4675 		pr_err("error %d\n", rc);  in init_agc()
4678 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);  in init_agc()
4679 	if (rc != 0) {  in init_agc()
4680 		pr_err("error %d\n", rc);  in init_agc()
4683 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);  in init_agc()
4684 	if (rc != 0) {  in init_agc()
4685 		pr_err("error %d\n", rc);  in init_agc()
4688 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);  in init_agc()
4689 	if (rc != 0) {  in init_agc()
4690 		pr_err("error %d\n", rc);  in init_agc()
4693 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);  in init_agc()
4694 	if (rc != 0) {  in init_agc()
4695 		pr_err("error %d\n", rc);  in init_agc()
4698 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);  in init_agc()
4699 	if (rc != 0) {  in init_agc()
4700 		pr_err("error %d\n", rc);  in init_agc()
4703 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);  in init_agc()
4704 	if (rc != 0) {  in init_agc()
4705 		pr_err("error %d\n", rc);  in init_agc()
4708 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);  in init_agc()
4709 	if (rc != 0) {  in init_agc()
4710 		pr_err("error %d\n", rc);  in init_agc()
4722 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);  in init_agc()
4723 	if (rc != 0) {  in init_agc()
4724 		pr_err("error %d\n", rc);  in init_agc()
4727 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);  in init_agc()
4728 	if (rc != 0) {  in init_agc()
4729 		pr_err("error %d\n", rc);  in init_agc()
4734 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in init_agc()
4735 	if (rc != 0) {  in init_agc()
4736 		pr_err("error %d\n", rc);  in init_agc()
4741 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in init_agc()
4742 	if (rc != 0) {  in init_agc()
4743 		pr_err("error %d\n", rc);  in init_agc()
4749 	return rc;  in init_agc()
4766 	int rc;  in set_frequency()  local
4837 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);  in set_frequency()
4838 	if (rc != 0) {  in set_frequency()
4839 		pr_err("error %d\n", rc);  in set_frequency()
4847 	return rc;  in set_frequency()
4863 	int rc;  in get_acc_pkt_err()  local
4873 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);  in get_acc_pkt_err()
4874 	if (rc != 0) {  in get_acc_pkt_err()
4875 		pr_err("error %d\n", rc);  in get_acc_pkt_err()
4895 	return rc;  in get_acc_pkt_err()
4916 	int rc;  in set_agc_rf()  local
4944 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_rf()
4945 			if (rc != 0) {  in set_agc_rf()
4946 				pr_err("error %d\n", rc);  in set_agc_rf()
4950 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_rf()
4951 			if (rc != 0) {  in set_agc_rf()
4952 				pr_err("error %d\n", rc);  in set_agc_rf()
4957 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_rf()
4958 			if (rc != 0) {  in set_agc_rf()
4959 				pr_err("error %d\n", rc);  in set_agc_rf()
4974 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_rf()
4975 			if (rc != 0) {  in set_agc_rf()
4976 				pr_err("error %d\n", rc);  in set_agc_rf()
4981 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);  in set_agc_rf()
4982 			if (rc != 0) {  in set_agc_rf()
4983 				pr_err("error %d\n", rc);  in set_agc_rf()
4987 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG…  in set_agc_rf()
4988 			if (rc != 0) {  in set_agc_rf()
4989 				pr_err("error %d\n", rc);  in set_agc_rf()
5004 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);  in set_agc_rf()
5005 				if (rc != 0) {  in set_agc_rf()
5006 					pr_err("error %d\n", rc);  in set_agc_rf()
5009 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);  in set_agc_rf()
5010 				if (rc != 0) {  in set_agc_rf()
5011 					pr_err("error %d\n", rc);  in set_agc_rf()
5017 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);  in set_agc_rf()
5018 			if (rc != 0) {  in set_agc_rf()
5019 				pr_err("error %d\n", rc);  in set_agc_rf()
5026 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_rf()
5027 			if (rc != 0) {  in set_agc_rf()
5028 				pr_err("error %d\n", rc);  in set_agc_rf()
5032 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_rf()
5033 			if (rc != 0) {  in set_agc_rf()
5034 				pr_err("error %d\n", rc);  in set_agc_rf()
5039 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_rf()
5040 			if (rc != 0) {  in set_agc_rf()
5041 				pr_err("error %d\n", rc);  in set_agc_rf()
5049 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_rf()
5050 			if (rc != 0) {  in set_agc_rf()
5051 				pr_err("error %d\n", rc);  in set_agc_rf()
5056 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);  in set_agc_rf()
5057 			if (rc != 0) {  in set_agc_rf()
5058 				pr_err("error %d\n", rc);  in set_agc_rf()
5065 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_rf()
5066 			if (rc != 0) {  in set_agc_rf()
5067 				pr_err("error %d\n", rc);  in set_agc_rf()
5071 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_rf()
5072 			if (rc != 0) {  in set_agc_rf()
5073 				pr_err("error %d\n", rc);  in set_agc_rf()
5078 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_rf()
5079 			if (rc != 0) {  in set_agc_rf()
5080 				pr_err("error %d\n", rc);  in set_agc_rf()
5084 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_rf()
5085 			if (rc != 0) {  in set_agc_rf()
5086 				pr_err("error %d\n", rc);  in set_agc_rf()
5113 	return rc;  in set_agc_rf()
5132 	int rc;  in set_agc_if()  local
5157 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_if()
5158 			if (rc != 0) {  in set_agc_if()
5159 				pr_err("error %d\n", rc);  in set_agc_if()
5163 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_if()
5164 			if (rc != 0) {  in set_agc_if()
5165 				pr_err("error %d\n", rc);  in set_agc_if()
5170 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_if()
5171 			if (rc != 0) {  in set_agc_if()
5172 				pr_err("error %d\n", rc);  in set_agc_if()
5188 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_if()
5189 			if (rc != 0) {  in set_agc_if()
5190 				pr_err("error %d\n", rc);  in set_agc_if()
5195 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);  in set_agc_if()
5196 			if (rc != 0) {  in set_agc_if()
5197 				pr_err("error %d\n", rc);  in set_agc_if()
5201 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA…  in set_agc_if()
5202 			if (rc != 0) {  in set_agc_if()
5203 				pr_err("error %d\n", rc);  in set_agc_if()
5218 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);  in set_agc_if()
5219 				if (rc != 0) {  in set_agc_if()
5220 					pr_err("error %d\n", rc);  in set_agc_if()
5223 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);  in set_agc_if()
5224 				if (rc != 0) {  in set_agc_if()
5225 					pr_err("error %d\n", rc);  in set_agc_if()
5229 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);  in set_agc_if()
5230 				if (rc != 0) {  in set_agc_if()
5231 					pr_err("error %d\n", rc);  in set_agc_if()
5234 				rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);  in set_agc_if()
5235 				if (rc != 0) {  in set_agc_if()
5236 					pr_err("error %d\n", rc);  in set_agc_if()
5245 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_if()
5246 			if (rc != 0) {  in set_agc_if()
5247 				pr_err("error %d\n", rc);  in set_agc_if()
5251 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_if()
5252 			if (rc != 0) {  in set_agc_if()
5253 				pr_err("error %d\n", rc);  in set_agc_if()
5258 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_if()
5259 			if (rc != 0) {  in set_agc_if()
5260 				pr_err("error %d\n", rc);  in set_agc_if()
5269 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_if()
5270 			if (rc != 0) {  in set_agc_if()
5271 				pr_err("error %d\n", rc);  in set_agc_if()
5276 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);  in set_agc_if()
5277 			if (rc != 0) {  in set_agc_if()
5278 				pr_err("error %d\n", rc);  in set_agc_if()
5286 			rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_agc_if()
5287 			if (rc != 0) {  in set_agc_if()
5288 				pr_err("error %d\n", rc);  in set_agc_if()
5292 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_agc_if()
5293 			if (rc != 0) {  in set_agc_if()
5294 				pr_err("error %d\n", rc);  in set_agc_if()
5299 			rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);  in set_agc_if()
5300 			if (rc != 0) {  in set_agc_if()
5301 				pr_err("error %d\n", rc);  in set_agc_if()
5306 			rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);  in set_agc_if()
5307 			if (rc != 0) {  in set_agc_if()
5308 				pr_err("error %d\n", rc);  in set_agc_if()
5317 		rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);  in set_agc_if()
5318 		if (rc != 0) {  in set_agc_if()
5319 			pr_err("error %d\n", rc);  in set_agc_if()
5342 	return rc;  in set_agc_if()
5356 	int rc;  in set_iqm_af()  local
5361 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);  in set_iqm_af()
5362 	if (rc != 0) {  in set_iqm_af()
5363 		pr_err("error %d\n", rc);  in set_iqm_af()
5370 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);  in set_iqm_af()
5371 	if (rc != 0) {  in set_iqm_af()
5372 		pr_err("error %d\n", rc);  in set_iqm_af()
5378 	return rc;  in set_iqm_af()
5408 	int rc;  in power_down_vsb()  local
5421 	rc = scu_command(dev_addr, &cmd_scu);  in power_down_vsb()
5422 	if (rc != 0) {  in power_down_vsb()
5423 		pr_err("error %d\n", rc);  in power_down_vsb()
5428 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in power_down_vsb()
5429 	if (rc != 0) {  in power_down_vsb()
5430 		pr_err("error %d\n", rc);  in power_down_vsb()
5433 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);  in power_down_vsb()
5434 	if (rc != 0) {  in power_down_vsb()
5435 		pr_err("error %d\n", rc);  in power_down_vsb()
5439 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);  in power_down_vsb()
5440 		if (rc != 0) {  in power_down_vsb()
5441 			pr_err("error %d\n", rc);  in power_down_vsb()
5444 		rc = set_iqm_af(demod, false);  in power_down_vsb()
5445 		if (rc != 0) {  in power_down_vsb()
5446 			pr_err("error %d\n", rc);  in power_down_vsb()
5450 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in power_down_vsb()
5451 		if (rc != 0) {  in power_down_vsb()
5452 			pr_err("error %d\n", rc);  in power_down_vsb()
5455 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in power_down_vsb()
5456 		if (rc != 0) {  in power_down_vsb()
5457 			pr_err("error %d\n", rc);  in power_down_vsb()
5460 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in power_down_vsb()
5461 		if (rc != 0) {  in power_down_vsb()
5462 			pr_err("error %d\n", rc);  in power_down_vsb()
5465 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in power_down_vsb()
5466 		if (rc != 0) {  in power_down_vsb()
5467 			pr_err("error %d\n", rc);  in power_down_vsb()
5470 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in power_down_vsb()
5471 		if (rc != 0) {  in power_down_vsb()
5472 			pr_err("error %d\n", rc);  in power_down_vsb()
5478 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in power_down_vsb()
5479 	if (rc != 0) {  in power_down_vsb()
5480 		pr_err("error %d\n", rc);  in power_down_vsb()
5486 	return rc;  in power_down_vsb()
5498 	int rc;  in set_vsb_leak_n_gain()  local
5689 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_g…  in set_vsb_leak_n_gain()
5690 	if (rc != 0) {  in set_vsb_leak_n_gain()
5691 		pr_err("error %d\n", rc);  in set_vsb_leak_n_gain()
5694 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_…  in set_vsb_leak_n_gain()
5695 	if (rc != 0) {  in set_vsb_leak_n_gain()
5696 		pr_err("error %d\n", rc);  in set_vsb_leak_n_gain()
5702 	return rc;  in set_vsb_leak_n_gain()
5715 	int rc;  in set_vsb()  local
5757 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in set_vsb()
5758 	if (rc != 0) {  in set_vsb()
5759 		pr_err("error %d\n", rc);  in set_vsb()
5762 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);  in set_vsb()
5763 	if (rc != 0) {  in set_vsb()
5764 		pr_err("error %d\n", rc);  in set_vsb()
5767 	rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in set_vsb()
5768 	if (rc != 0) {  in set_vsb()
5769 		pr_err("error %d\n", rc);  in set_vsb()
5772 	rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in set_vsb()
5773 	if (rc != 0) {  in set_vsb()
5774 		pr_err("error %d\n", rc);  in set_vsb()
5777 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in set_vsb()
5778 	if (rc != 0) {  in set_vsb()
5779 		pr_err("error %d\n", rc);  in set_vsb()
5782 	rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in set_vsb()
5783 	if (rc != 0) {  in set_vsb()
5784 		pr_err("error %d\n", rc);  in set_vsb()
5787 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in set_vsb()
5788 	if (rc != 0) {  in set_vsb()
5789 		pr_err("error %d\n", rc);  in set_vsb()
5800 	rc = scu_command(dev_addr, &cmd_scu);  in set_vsb()
5801 	if (rc != 0) {  in set_vsb()
5802 		pr_err("error %d\n", rc);  in set_vsb()
5806 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);  in set_vsb()
5807 	if (rc != 0) {  in set_vsb()
5808 		pr_err("error %d\n", rc);  in set_vsb()
5811 	rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);  in set_vsb()
5812 	if (rc != 0) {  in set_vsb()
5813 		pr_err("error %d\n", rc);  in set_vsb()
5816 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);  in set_vsb()
5817 	if (rc != 0) {  in set_vsb()
5818 		pr_err("error %d\n", rc);  in set_vsb()
5822 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);  in set_vsb()
5823 	if (rc != 0) {  in set_vsb()
5824 		pr_err("error %d\n", rc);  in set_vsb()
5827 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);  in set_vsb()
5828 	if (rc != 0) {  in set_vsb()
5829 		pr_err("error %d\n", rc);  in set_vsb()
5832 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);  in set_vsb()
5833 	if (rc != 0) {  in set_vsb()
5834 		pr_err("error %d\n", rc);  in set_vsb()
5838 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);  in set_vsb()
5839 	if (rc != 0) {  in set_vsb()
5840 		pr_err("error %d\n", rc);  in set_vsb()
5843 	rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);  in set_vsb()
5844 	if (rc != 0) {  in set_vsb()
5845 		pr_err("error %d\n", rc);  in set_vsb()
5848 	rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);  in set_vsb()
5849 	if (rc != 0) {  in set_vsb()
5850 		pr_err("error %d\n", rc);  in set_vsb()
5853 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);  in set_vsb()
5854 	if (rc != 0) {  in set_vsb()
5855 		pr_err("error %d\n", rc);  in set_vsb()
5858 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);  in set_vsb()
5859 	if (rc != 0) {  in set_vsb()
5860 		pr_err("error %d\n", rc);  in set_vsb()
5863 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);  in set_vsb()
5864 	if (rc != 0) {  in set_vsb()
5865 		pr_err("error %d\n", rc);  in set_vsb()
5868 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);  in set_vsb()
5869 	if (rc != 0) {  in set_vsb()
5870 		pr_err("error %d\n", rc);  in set_vsb()
5873 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);  in set_vsb()
5874 	if (rc != 0) {  in set_vsb()
5875 		pr_err("error %d\n", rc);  in set_vsb()
5878 	rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);  in set_vsb()
5879 	if (rc != 0) {  in set_vsb()
5880 		pr_err("error %d\n", rc);  in set_vsb()
5884 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)…  in set_vsb()
5885 	if (rc != 0) {  in set_vsb()
5886 		pr_err("error %d\n", rc);  in set_vsb()
5889 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)…  in set_vsb()
5890 	if (rc != 0) {  in set_vsb()
5891 		pr_err("error %d\n", rc);  in set_vsb()
5895 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);  in set_vsb()
5896 	if (rc != 0) {  in set_vsb()
5897 		pr_err("error %d\n", rc);  in set_vsb()
5900 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);  in set_vsb()
5901 	if (rc != 0) {  in set_vsb()
5902 		pr_err("error %d\n", rc);  in set_vsb()
5905 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);  in set_vsb()
5906 	if (rc != 0) {  in set_vsb()
5907 		pr_err("error %d\n", rc);  in set_vsb()
5910 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);  in set_vsb()
5911 	if (rc != 0) {  in set_vsb()
5912 		pr_err("error %d\n", rc);  in set_vsb()
5915 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);  in set_vsb()
5916 	if (rc != 0) {  in set_vsb()
5917 		pr_err("error %d\n", rc);  in set_vsb()
5920 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);  in set_vsb()
5921 	if (rc != 0) {  in set_vsb()
5922 		pr_err("error %d\n", rc);  in set_vsb()
5927 	rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);  in set_vsb()
5928 	if (rc != 0) {  in set_vsb()
5929 		pr_err("error %d\n", rc);  in set_vsb()
5934 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);  in set_vsb()
5935 		if (rc != 0) {  in set_vsb()
5936 			pr_err("error %d\n", rc);  in set_vsb()
5940 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_E…  in set_vsb()
5941 		if (rc != 0) {  in set_vsb()
5942 			pr_err("error %d\n", rc);  in set_vsb()
5948 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);  in set_vsb()
5949 	if (rc != 0) {  in set_vsb()
5950 		pr_err("error %d\n", rc);  in set_vsb()
5953 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);  in set_vsb()
5954 	if (rc != 0) {  in set_vsb()
5955 		pr_err("error %d\n", rc);  in set_vsb()
5958 	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);  in set_vsb()
5959 	if (rc != 0) {  in set_vsb()
5960 		pr_err("error %d\n", rc);  in set_vsb()
5963 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);  in set_vsb()
5964 	if (rc != 0) {  in set_vsb()
5965 		pr_err("error %d\n", rc);  in set_vsb()
5971 		rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);  in set_vsb()
5972 		if (rc != 0) {  in set_vsb()
5973 			pr_err("error %d\n", rc);  in set_vsb()
5976 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__…  in set_vsb()
5977 		if (rc != 0) {  in set_vsb()
5978 			pr_err("error %d\n", rc);  in set_vsb()
5983 	rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);  in set_vsb()
5984 	if (rc != 0) {  in set_vsb()
5985 		pr_err("error %d\n", rc);  in set_vsb()
5988 	rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);  in set_vsb()
5989 	if (rc != 0) {  in set_vsb()
5990 		pr_err("error %d\n", rc);  in set_vsb()
5993 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);  in set_vsb()
5994 	if (rc != 0) {  in set_vsb()
5995 		pr_err("error %d\n", rc);  in set_vsb()
5999 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);  in set_vsb()
6000 	if (rc != 0) {  in set_vsb()
6001 		pr_err("error %d\n", rc);  in set_vsb()
6004 …rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0…  in set_vsb()
6005 	if (rc != 0) {  in set_vsb()
6006 		pr_err("error %d\n", rc);  in set_vsb()
6011 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);  in set_vsb()
6012 	if (rc != 0) {  in set_vsb()
6013 		pr_err("error %d\n", rc);  in set_vsb()
6016 	rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);  in set_vsb()
6017 	if (rc != 0) {  in set_vsb()
6018 		pr_err("error %d\n", rc);  in set_vsb()
6021 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);  in set_vsb()
6022 	if (rc != 0) {  in set_vsb()
6023 		pr_err("error %d\n", rc);  in set_vsb()
6026 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);  in set_vsb()
6027 	if (rc != 0) {  in set_vsb()
6028 		pr_err("error %d\n", rc);  in set_vsb()
6032 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);  in set_vsb()
6033 	if (rc != 0) {  in set_vsb()
6034 		pr_err("error %d\n", rc);  in set_vsb()
6039 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);  in set_vsb()
6040 		if (rc != 0) {  in set_vsb()
6041 			pr_err("error %d\n", rc);  in set_vsb()
6047 	rc = set_iqm_af(demod, true);  in set_vsb()
6048 	if (rc != 0) {  in set_vsb()
6049 		pr_err("error %d\n", rc);  in set_vsb()
6052 	rc = adc_synchronization(demod);  in set_vsb()
6053 	if (rc != 0) {  in set_vsb()
6054 		pr_err("error %d\n", rc);  in set_vsb()
6058 	rc = init_agc(demod);  in set_vsb()
6059 	if (rc != 0) {  in set_vsb()
6060 		pr_err("error %d\n", rc);  in set_vsb()
6063 	rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);  in set_vsb()
6064 	if (rc != 0) {  in set_vsb()
6065 		pr_err("error %d\n", rc);  in set_vsb()
6068 	rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);  in set_vsb()
6069 	if (rc != 0) {  in set_vsb()
6070 		pr_err("error %d\n", rc);  in set_vsb()
6079 		rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);  in set_vsb()
6080 		if (rc != 0) {  in set_vsb()
6081 			pr_err("error %d\n", rc);  in set_vsb()
6085 	rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));  in set_vsb()
6086 	if (rc != 0) {  in set_vsb()
6087 		pr_err("error %d\n", rc);  in set_vsb()
6092 	rc = set_mpegtei_handling(demod);  in set_vsb()
6093 	if (rc != 0) {  in set_vsb()
6094 		pr_err("error %d\n", rc);  in set_vsb()
6097 	rc = bit_reverse_mpeg_output(demod);  in set_vsb()
6098 	if (rc != 0) {  in set_vsb()
6099 		pr_err("error %d\n", rc);  in set_vsb()
6102 	rc = set_mpeg_start_width(demod);  in set_vsb()
6103 	if (rc != 0) {  in set_vsb()
6104 		pr_err("error %d\n", rc);  in set_vsb()
6115 		rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in set_vsb()
6116 		if (rc != 0) {  in set_vsb()
6117 			pr_err("error %d\n", rc);  in set_vsb()
6130 	rc = scu_command(dev_addr, &cmd_scu);  in set_vsb()
6131 	if (rc != 0) {  in set_vsb()
6132 		pr_err("error %d\n", rc);  in set_vsb()
6136 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);  in set_vsb()
6137 	if (rc != 0) {  in set_vsb()
6138 		pr_err("error %d\n", rc);  in set_vsb()
6141 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);  in set_vsb()
6142 	if (rc != 0) {  in set_vsb()
6143 		pr_err("error %d\n", rc);  in set_vsb()
6146 …rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_S…  in set_vsb()
6147 	if (rc != 0) {  in set_vsb()
6148 		pr_err("error %d\n", rc);  in set_vsb()
6151 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);  in set_vsb()
6152 	if (rc != 0) {  in set_vsb()
6153 		pr_err("error %d\n", rc);  in set_vsb()
6156 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);  in set_vsb()
6157 	if (rc != 0) {  in set_vsb()
6158 		pr_err("error %d\n", rc);  in set_vsb()
6161 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);  in set_vsb()
6162 	if (rc != 0) {  in set_vsb()
6163 		pr_err("error %d\n", rc);  in set_vsb()
6166 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);  in set_vsb()
6167 	if (rc != 0) {  in set_vsb()
6168 		pr_err("error %d\n", rc);  in set_vsb()
6171 	rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);  in set_vsb()
6172 	if (rc != 0) {  in set_vsb()
6173 		pr_err("error %d\n", rc);  in set_vsb()
6184 	rc = scu_command(dev_addr, &cmd_scu);  in set_vsb()
6185 	if (rc != 0) {  in set_vsb()
6186 		pr_err("error %d\n", rc);  in set_vsb()
6190 	rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);  in set_vsb()
6191 	if (rc != 0) {  in set_vsb()
6192 		pr_err("error %d\n", rc);  in set_vsb()
6195 	rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);  in set_vsb()
6196 	if (rc != 0) {  in set_vsb()
6197 		pr_err("error %d\n", rc);  in set_vsb()
6200 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);  in set_vsb()
6201 	if (rc != 0) {  in set_vsb()
6202 		pr_err("error %d\n", rc);  in set_vsb()
6208 	return rc;  in set_vsb()
6219 	int rc;  in get_vsb_post_rs_pck_err()  local
6226 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);  in get_vsb_post_rs_pck_err()
6227 	if (rc != 0) {  in get_vsb_post_rs_pck_err()
6228 		pr_err("error %d\n", rc);  in get_vsb_post_rs_pck_err()
6247 	return rc;  in get_vsb_post_rs_pck_err()
6258 	int rc;  in get_vs_bpost_viterbi_ber()  local
6265 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);  in get_vs_bpost_viterbi_ber()
6266 	if (rc != 0) {  in get_vs_bpost_viterbi_ber()
6267 		pr_err("error %d\n", rc);  in get_vs_bpost_viterbi_ber()
6292 	return rc;  in get_vs_bpost_viterbi_ber()
6304 	int rc;  in get_vs_bpre_viterbi_ber()  local
6306 	rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);  in get_vs_bpre_viterbi_ber()
6307 	if (rc != 0) {  in get_vs_bpre_viterbi_ber()
6308 		pr_err("error %d\n", rc);  in get_vs_bpre_viterbi_ber()
6324 	int rc;  in get_vsbmer()  local
6327 	rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);  in get_vsbmer()
6328 	if (rc != 0) {  in get_vsbmer()
6329 		pr_err("error %d\n", rc);  in get_vsbmer()
6337 	return rc;  in get_vsbmer()
6366 	int rc;  in power_down_qam()  local
6377 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in power_down_qam()
6378 	if (rc != 0) {  in power_down_qam()
6379 		pr_err("error %d\n", rc);  in power_down_qam()
6382 	rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);  in power_down_qam()
6383 	if (rc != 0) {  in power_down_qam()
6384 		pr_err("error %d\n", rc);  in power_down_qam()
6394 	rc = scu_command(dev_addr, &cmd_scu);  in power_down_qam()
6395 	if (rc != 0) {  in power_down_qam()
6396 		pr_err("error %d\n", rc);  in power_down_qam()
6401 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);  in power_down_qam()
6402 		if (rc != 0) {  in power_down_qam()
6403 			pr_err("error %d\n", rc);  in power_down_qam()
6406 		rc = set_iqm_af(demod, false);  in power_down_qam()
6407 		if (rc != 0) {  in power_down_qam()
6408 			pr_err("error %d\n", rc);  in power_down_qam()
6412 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in power_down_qam()
6413 		if (rc != 0) {  in power_down_qam()
6414 			pr_err("error %d\n", rc);  in power_down_qam()
6417 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in power_down_qam()
6418 		if (rc != 0) {  in power_down_qam()
6419 			pr_err("error %d\n", rc);  in power_down_qam()
6422 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in power_down_qam()
6423 		if (rc != 0) {  in power_down_qam()
6424 			pr_err("error %d\n", rc);  in power_down_qam()
6427 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in power_down_qam()
6428 		if (rc != 0) {  in power_down_qam()
6429 			pr_err("error %d\n", rc);  in power_down_qam()
6432 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in power_down_qam()
6433 		if (rc != 0) {  in power_down_qam()
6434 			pr_err("error %d\n", rc);  in power_down_qam()
6442 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in power_down_qam()
6443 	if (rc != 0) {  in power_down_qam()
6444 		pr_err("error %d\n", rc);  in power_down_qam()
6450 	return rc;  in power_down_qam()
6478 	int rc;  in set_qam_measurement()  local
6572 	rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);  in set_qam_measurement()
6573 	if (rc != 0) {  in set_qam_measurement()
6574 		pr_err("error %d\n", rc);  in set_qam_measurement()
6577 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);  in set_qam_measurement()
6578 	if (rc != 0) {  in set_qam_measurement()
6579 		pr_err("error %d\n", rc);  in set_qam_measurement()
6582 	rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);  in set_qam_measurement()
6583 	if (rc != 0) {  in set_qam_measurement()
6584 		pr_err("error %d\n", rc);  in set_qam_measurement()
6589 	rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);  in set_qam_measurement()
6590 	if (rc != 0) {  in set_qam_measurement()
6591 		pr_err("error %d\n", rc);  in set_qam_measurement()
6594 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);  in set_qam_measurement()
6595 	if (rc != 0) {  in set_qam_measurement()
6596 		pr_err("error %d\n", rc);  in set_qam_measurement()
6599 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);  in set_qam_measurement()
6600 	if (rc != 0) {  in set_qam_measurement()
6601 		pr_err("error %d\n", rc);  in set_qam_measurement()
6646 		rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);  in set_qam_measurement()
6647 		if (rc != 0) {  in set_qam_measurement()
6648 			pr_err("error %d\n", rc);  in set_qam_measurement()
6651 		rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);  in set_qam_measurement()
6652 		if (rc != 0) {  in set_qam_measurement()
6653 			pr_err("error %d\n", rc);  in set_qam_measurement()
6662 	return rc;  in set_qam_measurement()
6676 	int rc;  in set_qam16()  local
6694 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam16()
6695 	if (rc != 0) {  in set_qam16()
6696 		pr_err("error %d\n", rc);  in set_qam16()
6699 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam16()
6700 	if (rc != 0) {  in set_qam16()
6701 		pr_err("error %d\n", rc);  in set_qam16()
6705 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);  in set_qam16()
6706 	if (rc != 0) {  in set_qam16()
6707 		pr_err("error %d\n", rc);  in set_qam16()
6710 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);  in set_qam16()
6711 	if (rc != 0) {  in set_qam16()
6712 		pr_err("error %d\n", rc);  in set_qam16()
6715 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);  in set_qam16()
6716 	if (rc != 0) {  in set_qam16()
6717 		pr_err("error %d\n", rc);  in set_qam16()
6720 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);  in set_qam16()
6721 	if (rc != 0) {  in set_qam16()
6722 		pr_err("error %d\n", rc);  in set_qam16()
6725 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);  in set_qam16()
6726 	if (rc != 0) {  in set_qam16()
6727 		pr_err("error %d\n", rc);  in set_qam16()
6730 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);  in set_qam16()
6731 	if (rc != 0) {  in set_qam16()
6732 		pr_err("error %d\n", rc);  in set_qam16()
6736 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam16()
6737 	if (rc != 0) {  in set_qam16()
6738 		pr_err("error %d\n", rc);  in set_qam16()
6741 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);  in set_qam16()
6742 	if (rc != 0) {  in set_qam16()
6743 		pr_err("error %d\n", rc);  in set_qam16()
6746 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam16()
6747 	if (rc != 0) {  in set_qam16()
6748 		pr_err("error %d\n", rc);  in set_qam16()
6752 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);  in set_qam16()
6753 	if (rc != 0) {  in set_qam16()
6754 		pr_err("error %d\n", rc);  in set_qam16()
6757 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);  in set_qam16()
6758 	if (rc != 0) {  in set_qam16()
6759 		pr_err("error %d\n", rc);  in set_qam16()
6762 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);  in set_qam16()
6763 	if (rc != 0) {  in set_qam16()
6764 		pr_err("error %d\n", rc);  in set_qam16()
6767 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);  in set_qam16()
6768 	if (rc != 0) {  in set_qam16()
6769 		pr_err("error %d\n", rc);  in set_qam16()
6772 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);  in set_qam16()
6773 	if (rc != 0) {  in set_qam16()
6774 		pr_err("error %d\n", rc);  in set_qam16()
6777 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);  in set_qam16()
6778 	if (rc != 0) {  in set_qam16()
6779 		pr_err("error %d\n", rc);  in set_qam16()
6782 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);  in set_qam16()
6783 	if (rc != 0) {  in set_qam16()
6784 		pr_err("error %d\n", rc);  in set_qam16()
6788 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam16()
6789 	if (rc != 0) {  in set_qam16()
6790 		pr_err("error %d\n", rc);  in set_qam16()
6793 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam16()
6794 	if (rc != 0) {  in set_qam16()
6795 		pr_err("error %d\n", rc);  in set_qam16()
6798 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam16()
6799 	if (rc != 0) {  in set_qam16()
6800 		pr_err("error %d\n", rc);  in set_qam16()
6803 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);  in set_qam16()
6804 	if (rc != 0) {  in set_qam16()
6805 		pr_err("error %d\n", rc);  in set_qam16()
6808 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam16()
6809 	if (rc != 0) {  in set_qam16()
6810 		pr_err("error %d\n", rc);  in set_qam16()
6813 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam16()
6814 	if (rc != 0) {  in set_qam16()
6815 		pr_err("error %d\n", rc);  in set_qam16()
6818 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);  in set_qam16()
6819 	if (rc != 0) {  in set_qam16()
6820 		pr_err("error %d\n", rc);  in set_qam16()
6823 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);  in set_qam16()
6824 	if (rc != 0) {  in set_qam16()
6825 		pr_err("error %d\n", rc);  in set_qam16()
6828 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam16()
6829 	if (rc != 0) {  in set_qam16()
6830 		pr_err("error %d\n", rc);  in set_qam16()
6833 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam16()
6834 	if (rc != 0) {  in set_qam16()
6835 		pr_err("error %d\n", rc);  in set_qam16()
6838 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam16()
6839 	if (rc != 0) {  in set_qam16()
6840 		pr_err("error %d\n", rc);  in set_qam16()
6843 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam16()
6844 	if (rc != 0) {  in set_qam16()
6845 		pr_err("error %d\n", rc);  in set_qam16()
6848 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam16()
6849 	if (rc != 0) {  in set_qam16()
6850 		pr_err("error %d\n", rc);  in set_qam16()
6853 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam16()
6854 	if (rc != 0) {  in set_qam16()
6855 		pr_err("error %d\n", rc);  in set_qam16()
6858 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam16()
6859 	if (rc != 0) {  in set_qam16()
6860 		pr_err("error %d\n", rc);  in set_qam16()
6863 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);  in set_qam16()
6864 	if (rc != 0) {  in set_qam16()
6865 		pr_err("error %d\n", rc);  in set_qam16()
6868 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);  in set_qam16()
6869 	if (rc != 0) {  in set_qam16()
6870 		pr_err("error %d\n", rc);  in set_qam16()
6873 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam16()
6874 	if (rc != 0) {  in set_qam16()
6875 		pr_err("error %d\n", rc);  in set_qam16()
6878 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam16()
6879 	if (rc != 0) {  in set_qam16()
6880 		pr_err("error %d\n", rc);  in set_qam16()
6883 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);  in set_qam16()
6884 	if (rc != 0) {  in set_qam16()
6885 		pr_err("error %d\n", rc);  in set_qam16()
6889 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);  in set_qam16()
6890 	if (rc != 0) {  in set_qam16()
6891 		pr_err("error %d\n", rc);  in set_qam16()
6897 	return rc;  in set_qam16()
6911 	int rc;  in set_qam32()  local
6929 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam32()
6930 	if (rc != 0) {  in set_qam32()
6931 		pr_err("error %d\n", rc);  in set_qam32()
6934 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam32()
6935 	if (rc != 0) {  in set_qam32()
6936 		pr_err("error %d\n", rc);  in set_qam32()
6940 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);  in set_qam32()
6941 	if (rc != 0) {  in set_qam32()
6942 		pr_err("error %d\n", rc);  in set_qam32()
6945 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);  in set_qam32()
6946 	if (rc != 0) {  in set_qam32()
6947 		pr_err("error %d\n", rc);  in set_qam32()
6950 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam32()
6951 	if (rc != 0) {  in set_qam32()
6952 		pr_err("error %d\n", rc);  in set_qam32()
6955 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);  in set_qam32()
6956 	if (rc != 0) {  in set_qam32()
6957 		pr_err("error %d\n", rc);  in set_qam32()
6960 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam32()
6961 	if (rc != 0) {  in set_qam32()
6962 		pr_err("error %d\n", rc);  in set_qam32()
6965 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);  in set_qam32()
6966 	if (rc != 0) {  in set_qam32()
6967 		pr_err("error %d\n", rc);  in set_qam32()
6971 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam32()
6972 	if (rc != 0) {  in set_qam32()
6973 		pr_err("error %d\n", rc);  in set_qam32()
6976 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);  in set_qam32()
6977 	if (rc != 0) {  in set_qam32()
6978 		pr_err("error %d\n", rc);  in set_qam32()
6981 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam32()
6982 	if (rc != 0) {  in set_qam32()
6983 		pr_err("error %d\n", rc);  in set_qam32()
6987 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);  in set_qam32()
6988 	if (rc != 0) {  in set_qam32()
6989 		pr_err("error %d\n", rc);  in set_qam32()
6992 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);  in set_qam32()
6993 	if (rc != 0) {  in set_qam32()
6994 		pr_err("error %d\n", rc);  in set_qam32()
6997 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);  in set_qam32()
6998 	if (rc != 0) {  in set_qam32()
6999 		pr_err("error %d\n", rc);  in set_qam32()
7002 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);  in set_qam32()
7003 	if (rc != 0) {  in set_qam32()
7004 		pr_err("error %d\n", rc);  in set_qam32()
7007 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);  in set_qam32()
7008 	if (rc != 0) {  in set_qam32()
7009 		pr_err("error %d\n", rc);  in set_qam32()
7012 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);  in set_qam32()
7013 	if (rc != 0) {  in set_qam32()
7014 		pr_err("error %d\n", rc);  in set_qam32()
7017 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);  in set_qam32()
7018 	if (rc != 0) {  in set_qam32()
7019 		pr_err("error %d\n", rc);  in set_qam32()
7023 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam32()
7024 	if (rc != 0) {  in set_qam32()
7025 		pr_err("error %d\n", rc);  in set_qam32()
7028 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam32()
7029 	if (rc != 0) {  in set_qam32()
7030 		pr_err("error %d\n", rc);  in set_qam32()
7033 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam32()
7034 	if (rc != 0) {  in set_qam32()
7035 		pr_err("error %d\n", rc);  in set_qam32()
7038 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);  in set_qam32()
7039 	if (rc != 0) {  in set_qam32()
7040 		pr_err("error %d\n", rc);  in set_qam32()
7043 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam32()
7044 	if (rc != 0) {  in set_qam32()
7045 		pr_err("error %d\n", rc);  in set_qam32()
7048 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam32()
7049 	if (rc != 0) {  in set_qam32()
7050 		pr_err("error %d\n", rc);  in set_qam32()
7053 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);  in set_qam32()
7054 	if (rc != 0) {  in set_qam32()
7055 		pr_err("error %d\n", rc);  in set_qam32()
7058 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);  in set_qam32()
7059 	if (rc != 0) {  in set_qam32()
7060 		pr_err("error %d\n", rc);  in set_qam32()
7063 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam32()
7064 	if (rc != 0) {  in set_qam32()
7065 		pr_err("error %d\n", rc);  in set_qam32()
7068 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam32()
7069 	if (rc != 0) {  in set_qam32()
7070 		pr_err("error %d\n", rc);  in set_qam32()
7073 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam32()
7074 	if (rc != 0) {  in set_qam32()
7075 		pr_err("error %d\n", rc);  in set_qam32()
7078 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam32()
7079 	if (rc != 0) {  in set_qam32()
7080 		pr_err("error %d\n", rc);  in set_qam32()
7083 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam32()
7084 	if (rc != 0) {  in set_qam32()
7085 		pr_err("error %d\n", rc);  in set_qam32()
7088 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam32()
7089 	if (rc != 0) {  in set_qam32()
7090 		pr_err("error %d\n", rc);  in set_qam32()
7093 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam32()
7094 	if (rc != 0) {  in set_qam32()
7095 		pr_err("error %d\n", rc);  in set_qam32()
7098 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);  in set_qam32()
7099 	if (rc != 0) {  in set_qam32()
7100 		pr_err("error %d\n", rc);  in set_qam32()
7103 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);  in set_qam32()
7104 	if (rc != 0) {  in set_qam32()
7105 		pr_err("error %d\n", rc);  in set_qam32()
7108 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam32()
7109 	if (rc != 0) {  in set_qam32()
7110 		pr_err("error %d\n", rc);  in set_qam32()
7113 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam32()
7114 	if (rc != 0) {  in set_qam32()
7115 		pr_err("error %d\n", rc);  in set_qam32()
7118 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);  in set_qam32()
7119 	if (rc != 0) {  in set_qam32()
7120 		pr_err("error %d\n", rc);  in set_qam32()
7124 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);  in set_qam32()
7125 	if (rc != 0) {  in set_qam32()
7126 		pr_err("error %d\n", rc);  in set_qam32()
7132 	return rc;  in set_qam32()
7146 	int rc;  in set_qam64()  local
7165 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam64()
7166 	if (rc != 0) {  in set_qam64()
7167 		pr_err("error %d\n", rc);  in set_qam64()
7170 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam64()
7171 	if (rc != 0) {  in set_qam64()
7172 		pr_err("error %d\n", rc);  in set_qam64()
7176 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);  in set_qam64()
7177 	if (rc != 0) {  in set_qam64()
7178 		pr_err("error %d\n", rc);  in set_qam64()
7181 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);  in set_qam64()
7182 	if (rc != 0) {  in set_qam64()
7183 		pr_err("error %d\n", rc);  in set_qam64()
7186 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam64()
7187 	if (rc != 0) {  in set_qam64()
7188 		pr_err("error %d\n", rc);  in set_qam64()
7191 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);  in set_qam64()
7192 	if (rc != 0) {  in set_qam64()
7193 		pr_err("error %d\n", rc);  in set_qam64()
7196 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam64()
7197 	if (rc != 0) {  in set_qam64()
7198 		pr_err("error %d\n", rc);  in set_qam64()
7201 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);  in set_qam64()
7202 	if (rc != 0) {  in set_qam64()
7203 		pr_err("error %d\n", rc);  in set_qam64()
7207 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam64()
7208 	if (rc != 0) {  in set_qam64()
7209 		pr_err("error %d\n", rc);  in set_qam64()
7212 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);  in set_qam64()
7213 	if (rc != 0) {  in set_qam64()
7214 		pr_err("error %d\n", rc);  in set_qam64()
7217 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam64()
7218 	if (rc != 0) {  in set_qam64()
7219 		pr_err("error %d\n", rc);  in set_qam64()
7223 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);  in set_qam64()
7224 	if (rc != 0) {  in set_qam64()
7225 		pr_err("error %d\n", rc);  in set_qam64()
7228 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);  in set_qam64()
7229 	if (rc != 0) {  in set_qam64()
7230 		pr_err("error %d\n", rc);  in set_qam64()
7233 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);  in set_qam64()
7234 	if (rc != 0) {  in set_qam64()
7235 		pr_err("error %d\n", rc);  in set_qam64()
7238 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);  in set_qam64()
7239 	if (rc != 0) {  in set_qam64()
7240 		pr_err("error %d\n", rc);  in set_qam64()
7243 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);  in set_qam64()
7244 	if (rc != 0) {  in set_qam64()
7245 		pr_err("error %d\n", rc);  in set_qam64()
7248 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);  in set_qam64()
7249 	if (rc != 0) {  in set_qam64()
7250 		pr_err("error %d\n", rc);  in set_qam64()
7253 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);  in set_qam64()
7254 	if (rc != 0) {  in set_qam64()
7255 		pr_err("error %d\n", rc);  in set_qam64()
7259 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam64()
7260 	if (rc != 0) {  in set_qam64()
7261 		pr_err("error %d\n", rc);  in set_qam64()
7264 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam64()
7265 	if (rc != 0) {  in set_qam64()
7266 		pr_err("error %d\n", rc);  in set_qam64()
7269 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam64()
7270 	if (rc != 0) {  in set_qam64()
7271 		pr_err("error %d\n", rc);  in set_qam64()
7274 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);  in set_qam64()
7275 	if (rc != 0) {  in set_qam64()
7276 		pr_err("error %d\n", rc);  in set_qam64()
7279 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam64()
7280 	if (rc != 0) {  in set_qam64()
7281 		pr_err("error %d\n", rc);  in set_qam64()
7284 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam64()
7285 	if (rc != 0) {  in set_qam64()
7286 		pr_err("error %d\n", rc);  in set_qam64()
7289 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);  in set_qam64()
7290 	if (rc != 0) {  in set_qam64()
7291 		pr_err("error %d\n", rc);  in set_qam64()
7294 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);  in set_qam64()
7295 	if (rc != 0) {  in set_qam64()
7296 		pr_err("error %d\n", rc);  in set_qam64()
7299 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam64()
7300 	if (rc != 0) {  in set_qam64()
7301 		pr_err("error %d\n", rc);  in set_qam64()
7304 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam64()
7305 	if (rc != 0) {  in set_qam64()
7306 		pr_err("error %d\n", rc);  in set_qam64()
7309 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam64()
7310 	if (rc != 0) {  in set_qam64()
7311 		pr_err("error %d\n", rc);  in set_qam64()
7314 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam64()
7315 	if (rc != 0) {  in set_qam64()
7316 		pr_err("error %d\n", rc);  in set_qam64()
7319 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam64()
7320 	if (rc != 0) {  in set_qam64()
7321 		pr_err("error %d\n", rc);  in set_qam64()
7324 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam64()
7325 	if (rc != 0) {  in set_qam64()
7326 		pr_err("error %d\n", rc);  in set_qam64()
7329 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam64()
7330 	if (rc != 0) {  in set_qam64()
7331 		pr_err("error %d\n", rc);  in set_qam64()
7334 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);  in set_qam64()
7335 	if (rc != 0) {  in set_qam64()
7336 		pr_err("error %d\n", rc);  in set_qam64()
7339 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);  in set_qam64()
7340 	if (rc != 0) {  in set_qam64()
7341 		pr_err("error %d\n", rc);  in set_qam64()
7344 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam64()
7345 	if (rc != 0) {  in set_qam64()
7346 		pr_err("error %d\n", rc);  in set_qam64()
7349 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam64()
7350 	if (rc != 0) {  in set_qam64()
7351 		pr_err("error %d\n", rc);  in set_qam64()
7354 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);  in set_qam64()
7355 	if (rc != 0) {  in set_qam64()
7356 		pr_err("error %d\n", rc);  in set_qam64()
7360 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);  in set_qam64()
7361 	if (rc != 0) {  in set_qam64()
7362 		pr_err("error %d\n", rc);  in set_qam64()
7368 	return rc;  in set_qam64()
7382 	int rc;  in set_qam128()  local
7400 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam128()
7401 	if (rc != 0) {  in set_qam128()
7402 		pr_err("error %d\n", rc);  in set_qam128()
7405 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam128()
7406 	if (rc != 0) {  in set_qam128()
7407 		pr_err("error %d\n", rc);  in set_qam128()
7411 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);  in set_qam128()
7412 	if (rc != 0) {  in set_qam128()
7413 		pr_err("error %d\n", rc);  in set_qam128()
7416 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);  in set_qam128()
7417 	if (rc != 0) {  in set_qam128()
7418 		pr_err("error %d\n", rc);  in set_qam128()
7421 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam128()
7422 	if (rc != 0) {  in set_qam128()
7423 		pr_err("error %d\n", rc);  in set_qam128()
7426 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);  in set_qam128()
7427 	if (rc != 0) {  in set_qam128()
7428 		pr_err("error %d\n", rc);  in set_qam128()
7431 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam128()
7432 	if (rc != 0) {  in set_qam128()
7433 		pr_err("error %d\n", rc);  in set_qam128()
7436 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);  in set_qam128()
7437 	if (rc != 0) {  in set_qam128()
7438 		pr_err("error %d\n", rc);  in set_qam128()
7442 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam128()
7443 	if (rc != 0) {  in set_qam128()
7444 		pr_err("error %d\n", rc);  in set_qam128()
7447 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);  in set_qam128()
7448 	if (rc != 0) {  in set_qam128()
7449 		pr_err("error %d\n", rc);  in set_qam128()
7452 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam128()
7453 	if (rc != 0) {  in set_qam128()
7454 		pr_err("error %d\n", rc);  in set_qam128()
7458 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);  in set_qam128()
7459 	if (rc != 0) {  in set_qam128()
7460 		pr_err("error %d\n", rc);  in set_qam128()
7463 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);  in set_qam128()
7464 	if (rc != 0) {  in set_qam128()
7465 		pr_err("error %d\n", rc);  in set_qam128()
7468 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);  in set_qam128()
7469 	if (rc != 0) {  in set_qam128()
7470 		pr_err("error %d\n", rc);  in set_qam128()
7473 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);  in set_qam128()
7474 	if (rc != 0) {  in set_qam128()
7475 		pr_err("error %d\n", rc);  in set_qam128()
7478 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);  in set_qam128()
7479 	if (rc != 0) {  in set_qam128()
7480 		pr_err("error %d\n", rc);  in set_qam128()
7483 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);  in set_qam128()
7484 	if (rc != 0) {  in set_qam128()
7485 		pr_err("error %d\n", rc);  in set_qam128()
7488 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);  in set_qam128()
7489 	if (rc != 0) {  in set_qam128()
7490 		pr_err("error %d\n", rc);  in set_qam128()
7494 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam128()
7495 	if (rc != 0) {  in set_qam128()
7496 		pr_err("error %d\n", rc);  in set_qam128()
7499 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam128()
7500 	if (rc != 0) {  in set_qam128()
7501 		pr_err("error %d\n", rc);  in set_qam128()
7504 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam128()
7505 	if (rc != 0) {  in set_qam128()
7506 		pr_err("error %d\n", rc);  in set_qam128()
7509 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);  in set_qam128()
7510 	if (rc != 0) {  in set_qam128()
7511 		pr_err("error %d\n", rc);  in set_qam128()
7514 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam128()
7515 	if (rc != 0) {  in set_qam128()
7516 		pr_err("error %d\n", rc);  in set_qam128()
7519 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam128()
7520 	if (rc != 0) {  in set_qam128()
7521 		pr_err("error %d\n", rc);  in set_qam128()
7524 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);  in set_qam128()
7525 	if (rc != 0) {  in set_qam128()
7526 		pr_err("error %d\n", rc);  in set_qam128()
7529 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);  in set_qam128()
7530 	if (rc != 0) {  in set_qam128()
7531 		pr_err("error %d\n", rc);  in set_qam128()
7534 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam128()
7535 	if (rc != 0) {  in set_qam128()
7536 		pr_err("error %d\n", rc);  in set_qam128()
7539 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam128()
7540 	if (rc != 0) {  in set_qam128()
7541 		pr_err("error %d\n", rc);  in set_qam128()
7544 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam128()
7545 	if (rc != 0) {  in set_qam128()
7546 		pr_err("error %d\n", rc);  in set_qam128()
7549 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam128()
7550 	if (rc != 0) {  in set_qam128()
7551 		pr_err("error %d\n", rc);  in set_qam128()
7554 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam128()
7555 	if (rc != 0) {  in set_qam128()
7556 		pr_err("error %d\n", rc);  in set_qam128()
7559 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam128()
7560 	if (rc != 0) {  in set_qam128()
7561 		pr_err("error %d\n", rc);  in set_qam128()
7564 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam128()
7565 	if (rc != 0) {  in set_qam128()
7566 		pr_err("error %d\n", rc);  in set_qam128()
7569 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);  in set_qam128()
7570 	if (rc != 0) {  in set_qam128()
7571 		pr_err("error %d\n", rc);  in set_qam128()
7574 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);  in set_qam128()
7575 	if (rc != 0) {  in set_qam128()
7576 		pr_err("error %d\n", rc);  in set_qam128()
7579 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam128()
7580 	if (rc != 0) {  in set_qam128()
7581 		pr_err("error %d\n", rc);  in set_qam128()
7584 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam128()
7585 	if (rc != 0) {  in set_qam128()
7586 		pr_err("error %d\n", rc);  in set_qam128()
7589 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);  in set_qam128()
7590 	if (rc != 0) {  in set_qam128()
7591 		pr_err("error %d\n", rc);  in set_qam128()
7595 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);  in set_qam128()
7596 	if (rc != 0) {  in set_qam128()
7597 		pr_err("error %d\n", rc);  in set_qam128()
7603 	return rc;  in set_qam128()
7617 	int rc;  in set_qam256()  local
7635 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq…  in set_qam256()
7636 	if (rc != 0) {  in set_qam256()
7637 		pr_err("error %d\n", rc);  in set_qam256()
7640 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)…  in set_qam256()
7641 	if (rc != 0) {  in set_qam256()
7642 		pr_err("error %d\n", rc);  in set_qam256()
7646 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);  in set_qam256()
7647 	if (rc != 0) {  in set_qam256()
7648 		pr_err("error %d\n", rc);  in set_qam256()
7651 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);  in set_qam256()
7652 	if (rc != 0) {  in set_qam256()
7653 		pr_err("error %d\n", rc);  in set_qam256()
7656 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);  in set_qam256()
7657 	if (rc != 0) {  in set_qam256()
7658 		pr_err("error %d\n", rc);  in set_qam256()
7661 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);  in set_qam256()
7662 	if (rc != 0) {  in set_qam256()
7663 		pr_err("error %d\n", rc);  in set_qam256()
7666 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);  in set_qam256()
7667 	if (rc != 0) {  in set_qam256()
7668 		pr_err("error %d\n", rc);  in set_qam256()
7671 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);  in set_qam256()
7672 	if (rc != 0) {  in set_qam256()
7673 		pr_err("error %d\n", rc);  in set_qam256()
7677 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);  in set_qam256()
7678 	if (rc != 0) {  in set_qam256()
7679 		pr_err("error %d\n", rc);  in set_qam256()
7682 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);  in set_qam256()
7683 	if (rc != 0) {  in set_qam256()
7684 		pr_err("error %d\n", rc);  in set_qam256()
7687 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);  in set_qam256()
7688 	if (rc != 0) {  in set_qam256()
7689 		pr_err("error %d\n", rc);  in set_qam256()
7693 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);  in set_qam256()
7694 	if (rc != 0) {  in set_qam256()
7695 		pr_err("error %d\n", rc);  in set_qam256()
7698 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);  in set_qam256()
7699 	if (rc != 0) {  in set_qam256()
7700 		pr_err("error %d\n", rc);  in set_qam256()
7703 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);  in set_qam256()
7704 	if (rc != 0) {  in set_qam256()
7705 		pr_err("error %d\n", rc);  in set_qam256()
7708 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);  in set_qam256()
7709 	if (rc != 0) {  in set_qam256()
7710 		pr_err("error %d\n", rc);  in set_qam256()
7713 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);  in set_qam256()
7714 	if (rc != 0) {  in set_qam256()
7715 		pr_err("error %d\n", rc);  in set_qam256()
7718 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);  in set_qam256()
7719 	if (rc != 0) {  in set_qam256()
7720 		pr_err("error %d\n", rc);  in set_qam256()
7723 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);  in set_qam256()
7724 	if (rc != 0) {  in set_qam256()
7725 		pr_err("error %d\n", rc);  in set_qam256()
7729 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);  in set_qam256()
7730 	if (rc != 0) {  in set_qam256()
7731 		pr_err("error %d\n", rc);  in set_qam256()
7734 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);  in set_qam256()
7735 	if (rc != 0) {  in set_qam256()
7736 		pr_err("error %d\n", rc);  in set_qam256()
7739 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);  in set_qam256()
7740 	if (rc != 0) {  in set_qam256()
7741 		pr_err("error %d\n", rc);  in set_qam256()
7744 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);  in set_qam256()
7745 	if (rc != 0) {  in set_qam256()
7746 		pr_err("error %d\n", rc);  in set_qam256()
7749 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);  in set_qam256()
7750 	if (rc != 0) {  in set_qam256()
7751 		pr_err("error %d\n", rc);  in set_qam256()
7754 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);  in set_qam256()
7755 	if (rc != 0) {  in set_qam256()
7756 		pr_err("error %d\n", rc);  in set_qam256()
7759 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);  in set_qam256()
7760 	if (rc != 0) {  in set_qam256()
7761 		pr_err("error %d\n", rc);  in set_qam256()
7764 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);  in set_qam256()
7765 	if (rc != 0) {  in set_qam256()
7766 		pr_err("error %d\n", rc);  in set_qam256()
7769 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);  in set_qam256()
7770 	if (rc != 0) {  in set_qam256()
7771 		pr_err("error %d\n", rc);  in set_qam256()
7774 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);  in set_qam256()
7775 	if (rc != 0) {  in set_qam256()
7776 		pr_err("error %d\n", rc);  in set_qam256()
7779 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);  in set_qam256()
7780 	if (rc != 0) {  in set_qam256()
7781 		pr_err("error %d\n", rc);  in set_qam256()
7784 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);  in set_qam256()
7785 	if (rc != 0) {  in set_qam256()
7786 		pr_err("error %d\n", rc);  in set_qam256()
7789 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);  in set_qam256()
7790 	if (rc != 0) {  in set_qam256()
7791 		pr_err("error %d\n", rc);  in set_qam256()
7794 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);  in set_qam256()
7795 	if (rc != 0) {  in set_qam256()
7796 		pr_err("error %d\n", rc);  in set_qam256()
7799 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);  in set_qam256()
7800 	if (rc != 0) {  in set_qam256()
7801 		pr_err("error %d\n", rc);  in set_qam256()
7804 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);  in set_qam256()
7805 	if (rc != 0) {  in set_qam256()
7806 		pr_err("error %d\n", rc);  in set_qam256()
7809 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);  in set_qam256()
7810 	if (rc != 0) {  in set_qam256()
7811 		pr_err("error %d\n", rc);  in set_qam256()
7814 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);  in set_qam256()
7815 	if (rc != 0) {  in set_qam256()
7816 		pr_err("error %d\n", rc);  in set_qam256()
7819 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);  in set_qam256()
7820 	if (rc != 0) {  in set_qam256()
7821 		pr_err("error %d\n", rc);  in set_qam256()
7824 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);  in set_qam256()
7825 	if (rc != 0) {  in set_qam256()
7826 		pr_err("error %d\n", rc);  in set_qam256()
7830 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);  in set_qam256()
7831 	if (rc != 0) {  in set_qam256()
7832 		pr_err("error %d\n", rc);  in set_qam256()
7838 	return rc;  in set_qam256()
7860 	int rc;  in set_qam()  local
8064 		rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);  in set_qam()
8065 		if (rc != 0) {  in set_qam()
8066 			pr_err("error %d\n", rc);  in set_qam()
8069 		rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);  in set_qam()
8070 		if (rc != 0) {  in set_qam()
8071 			pr_err("error %d\n", rc);  in set_qam()
8074 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in set_qam()
8075 		if (rc != 0) {  in set_qam()
8076 			pr_err("error %d\n", rc);  in set_qam()
8079 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in set_qam()
8080 		if (rc != 0) {  in set_qam()
8081 			pr_err("error %d\n", rc);  in set_qam()
8084 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in set_qam()
8085 		if (rc != 0) {  in set_qam()
8086 			pr_err("error %d\n", rc);  in set_qam()
8089 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in set_qam()
8090 		if (rc != 0) {  in set_qam()
8091 			pr_err("error %d\n", rc);  in set_qam()
8094 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in set_qam()
8095 		if (rc != 0) {  in set_qam()
8096 			pr_err("error %d\n", rc);  in set_qam()
8106 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8107 		if (rc != 0) {  in set_qam()
8108 			pr_err("error %d\n", rc);  in set_qam()
8125 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8126 		if (rc != 0) {  in set_qam()
8127 			pr_err("error %d\n", rc);  in set_qam()
8137 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8138 		if (rc != 0) {  in set_qam()
8139 			pr_err("error %d\n", rc);  in set_qam()
8143 		rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);  in set_qam()
8144 		if (rc != 0) {  in set_qam()
8145 			pr_err("error %d\n", rc);  in set_qam()
8149 		rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);  in set_qam()
8150 		if (rc != 0) {  in set_qam()
8151 			pr_err("error %d\n", rc);  in set_qam()
8160 		rc = set_frequency(demod, channel, tuner_freq_offset);  in set_qam()
8161 		if (rc != 0) {  in set_qam()
8162 			pr_err("error %d\n", rc);  in set_qam()
8169 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);  in set_qam()
8170 		if (rc != 0) {  in set_qam()
8171 			pr_err("error %d\n", rc);  in set_qam()
8174 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);  in set_qam()
8175 		if (rc != 0) {  in set_qam()
8176 			pr_err("error %d\n", rc);  in set_qam()
8183 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);  in set_qam()
8184 			if (rc != 0) {  in set_qam()
8185 				pr_err("error %d\n", rc);  in set_qam()
8189 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);  in set_qam()
8190 		if (rc != 0) {  in set_qam()
8191 			pr_err("error %d\n", rc);  in set_qam()
8194 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);  in set_qam()
8195 		if (rc != 0) {  in set_qam()
8196 			pr_err("error %d\n", rc);  in set_qam()
8199 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);  in set_qam()
8200 		if (rc != 0) {  in set_qam()
8201 			pr_err("error %d\n", rc);  in set_qam()
8205 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);  in set_qam()
8206 		if (rc != 0) {  in set_qam()
8207 			pr_err("error %d\n", rc);  in set_qam()
8211 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);  in set_qam()
8212 		if (rc != 0) {  in set_qam()
8213 			pr_err("error %d\n", rc);  in set_qam()
8216 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);  in set_qam()
8217 		if (rc != 0) {  in set_qam()
8218 			pr_err("error %d\n", rc);  in set_qam()
8221 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);  in set_qam()
8222 		if (rc != 0) {  in set_qam()
8223 			pr_err("error %d\n", rc);  in set_qam()
8226 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);  in set_qam()
8227 		if (rc != 0) {  in set_qam()
8228 			pr_err("error %d\n", rc);  in set_qam()
8231 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);  in set_qam()
8232 		if (rc != 0) {  in set_qam()
8233 			pr_err("error %d\n", rc);  in set_qam()
8236 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);  in set_qam()
8237 		if (rc != 0) {  in set_qam()
8238 			pr_err("error %d\n", rc);  in set_qam()
8241 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);  in set_qam()
8242 		if (rc != 0) {  in set_qam()
8243 			pr_err("error %d\n", rc);  in set_qam()
8247 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);  in set_qam()
8248 		if (rc != 0) {  in set_qam()
8249 			pr_err("error %d\n", rc);  in set_qam()
8252 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);  in set_qam()
8253 		if (rc != 0) {  in set_qam()
8254 			pr_err("error %d\n", rc);  in set_qam()
8258 		rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);  in set_qam()
8259 		if (rc != 0) {  in set_qam()
8260 			pr_err("error %d\n", rc);  in set_qam()
8264 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);  in set_qam()
8265 			if (rc != 0) {  in set_qam()
8266 				pr_err("error %d\n", rc);  in set_qam()
8269 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);  in set_qam()
8270 			if (rc != 0) {  in set_qam()
8271 				pr_err("error %d\n", rc);  in set_qam()
8274 			rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);  in set_qam()
8275 			if (rc != 0) {  in set_qam()
8276 				pr_err("error %d\n", rc);  in set_qam()
8284 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);  in set_qam()
8285 				if (rc != 0) {  in set_qam()
8286 					pr_err("error %d\n", rc);  in set_qam()
8289 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);  in set_qam()
8290 				if (rc != 0) {  in set_qam()
8291 					pr_err("error %d\n", rc);  in set_qam()
8294 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);  in set_qam()
8295 				if (rc != 0) {  in set_qam()
8296 					pr_err("error %d\n", rc);  in set_qam()
8302 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);  in set_qam()
8303 				if (rc != 0) {  in set_qam()
8304 					pr_err("error %d\n", rc);  in set_qam()
8307 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);  in set_qam()
8308 				if (rc != 0) {  in set_qam()
8309 					pr_err("error %d\n", rc);  in set_qam()
8312 				rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);  in set_qam()
8313 				if (rc != 0) {  in set_qam()
8314 					pr_err("error %d\n", rc);  in set_qam()
8323 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);  in set_qam()
8324 		if (rc != 0) {  in set_qam()
8325 			pr_err("error %d\n", rc);  in set_qam()
8328 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);  in set_qam()
8329 		if (rc != 0) {  in set_qam()
8330 			pr_err("error %d\n", rc);  in set_qam()
8333 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);  in set_qam()
8334 		if (rc != 0) {  in set_qam()
8335 			pr_err("error %d\n", rc);  in set_qam()
8338 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);  in set_qam()
8339 		if (rc != 0) {  in set_qam()
8340 			pr_err("error %d\n", rc);  in set_qam()
8343 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);  in set_qam()
8344 		if (rc != 0) {  in set_qam()
8345 			pr_err("error %d\n", rc);  in set_qam()
8348 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);  in set_qam()
8349 		if (rc != 0) {  in set_qam()
8350 			pr_err("error %d\n", rc);  in set_qam()
8353 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);  in set_qam()
8354 		if (rc != 0) {  in set_qam()
8355 			pr_err("error %d\n", rc);  in set_qam()
8358 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);  in set_qam()
8359 		if (rc != 0) {  in set_qam()
8360 			pr_err("error %d\n", rc);  in set_qam()
8363 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);  in set_qam()
8364 		if (rc != 0) {  in set_qam()
8365 			pr_err("error %d\n", rc);  in set_qam()
8368 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);  in set_qam()
8369 		if (rc != 0) {  in set_qam()
8370 			pr_err("error %d\n", rc);  in set_qam()
8373 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);  in set_qam()
8374 		if (rc != 0) {  in set_qam()
8375 			pr_err("error %d\n", rc);  in set_qam()
8378 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);  in set_qam()
8379 		if (rc != 0) {  in set_qam()
8380 			pr_err("error %d\n", rc);  in set_qam()
8383 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);  in set_qam()
8384 		if (rc != 0) {  in set_qam()
8385 			pr_err("error %d\n", rc);  in set_qam()
8388 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);  in set_qam()
8389 		if (rc != 0) {  in set_qam()
8390 			pr_err("error %d\n", rc);  in set_qam()
8393 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);  in set_qam()
8394 		if (rc != 0) {  in set_qam()
8395 			pr_err("error %d\n", rc);  in set_qam()
8398 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);  in set_qam()
8399 		if (rc != 0) {  in set_qam()
8400 			pr_err("error %d\n", rc);  in set_qam()
8403 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);  in set_qam()
8404 		if (rc != 0) {  in set_qam()
8405 			pr_err("error %d\n", rc);  in set_qam()
8408 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);  in set_qam()
8409 		if (rc != 0) {  in set_qam()
8410 			pr_err("error %d\n", rc);  in set_qam()
8413 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);  in set_qam()
8414 		if (rc != 0) {  in set_qam()
8415 			pr_err("error %d\n", rc);  in set_qam()
8418 		rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);  in set_qam()
8419 		if (rc != 0) {  in set_qam()
8420 			pr_err("error %d\n", rc);  in set_qam()
8424 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);  in set_qam()
8425 		if (rc != 0) {  in set_qam()
8426 			pr_err("error %d\n", rc);  in set_qam()
8429 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);  in set_qam()
8430 		if (rc != 0) {  in set_qam()
8431 			pr_err("error %d\n", rc);  in set_qam()
8434 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);  in set_qam()
8435 		if (rc != 0) {  in set_qam()
8436 			pr_err("error %d\n", rc);  in set_qam()
8439 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);  in set_qam()
8440 		if (rc != 0) {  in set_qam()
8441 			pr_err("error %d\n", rc);  in set_qam()
8444 		rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);  in set_qam()
8445 		if (rc != 0) {  in set_qam()
8446 			pr_err("error %d\n", rc);  in set_qam()
8453 		rc = set_iqm_af(demod, true);  in set_qam()
8454 		if (rc != 0) {  in set_qam()
8455 			pr_err("error %d\n", rc);  in set_qam()
8458 		rc = adc_synchronization(demod);  in set_qam()
8459 		if (rc != 0) {  in set_qam()
8460 			pr_err("error %d\n", rc);  in set_qam()
8464 		rc = init_agc(demod);  in set_qam()
8465 		if (rc != 0) {  in set_qam()
8466 			pr_err("error %d\n", rc);  in set_qam()
8469 		rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);  in set_qam()
8470 		if (rc != 0) {  in set_qam()
8471 			pr_err("error %d\n", rc);  in set_qam()
8474 		rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);  in set_qam()
8475 		if (rc != 0) {  in set_qam()
8476 			pr_err("error %d\n", rc);  in set_qam()
8485 			rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);  in set_qam()
8486 			if (rc != 0) {  in set_qam()
8487 				pr_err("error %d\n", rc);  in set_qam()
8491 		rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));  in set_qam()
8492 		if (rc != 0) {  in set_qam()
8493 			pr_err("error %d\n", rc);  in set_qam()
8500 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), …  in set_qam()
8501 			if (rc != 0) {  in set_qam()
8502 				pr_err("error %d\n", rc);  in set_qam()
8505 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), …  in set_qam()
8506 			if (rc != 0) {  in set_qam()
8507 				pr_err("error %d\n", rc);  in set_qam()
8513 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap…  in set_qam()
8514 				if (rc != 0) {  in set_qam()
8515 					pr_err("error %d\n", rc);  in set_qam()
8518 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap…  in set_qam()
8519 				if (rc != 0) {  in set_qam()
8520 					pr_err("error %d\n", rc);  in set_qam()
8525 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t…  in set_qam()
8526 				if (rc != 0) {  in set_qam()
8527 					pr_err("error %d\n", rc);  in set_qam()
8530 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t…  in set_qam()
8531 				if (rc != 0) {  in set_qam()
8532 					pr_err("error %d\n", rc);  in set_qam()
8540 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), …  in set_qam()
8541 			if (rc != 0) {  in set_qam()
8542 				pr_err("error %d\n", rc);  in set_qam()
8545 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), …  in set_qam()
8546 			if (rc != 0) {  in set_qam()
8547 				pr_err("error %d\n", rc);  in set_qam()
8555 			rc = set_qam16(demod);  in set_qam()
8556 			if (rc != 0) {  in set_qam()
8557 				pr_err("error %d\n", rc);  in set_qam()
8562 			rc = set_qam32(demod);  in set_qam()
8563 			if (rc != 0) {  in set_qam()
8564 				pr_err("error %d\n", rc);  in set_qam()
8569 			rc = set_qam64(demod);  in set_qam()
8570 			if (rc != 0) {  in set_qam()
8571 				pr_err("error %d\n", rc);  in set_qam()
8576 			rc = set_qam128(demod);  in set_qam()
8577 			if (rc != 0) {  in set_qam()
8578 				pr_err("error %d\n", rc);  in set_qam()
8583 			rc = set_qam256(demod);  in set_qam()
8584 			if (rc != 0) {  in set_qam()
8585 				pr_err("error %d\n", rc);  in set_qam()
8595 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);  in set_qam()
8596 		if (rc != 0) {  in set_qam()
8597 			pr_err("error %d\n", rc);  in set_qam()
8602 		rc = set_mpegtei_handling(demod);  in set_qam()
8603 		if (rc != 0) {  in set_qam()
8604 			pr_err("error %d\n", rc);  in set_qam()
8607 		rc = bit_reverse_mpeg_output(demod);  in set_qam()
8608 		if (rc != 0) {  in set_qam()
8609 			pr_err("error %d\n", rc);  in set_qam()
8612 		rc = set_mpeg_start_width(demod);  in set_qam()
8613 		if (rc != 0) {  in set_qam()
8614 			pr_err("error %d\n", rc);  in set_qam()
8625 			rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in set_qam()
8626 			if (rc != 0) {  in set_qam()
8627 				pr_err("error %d\n", rc);  in set_qam()
8642 		rc = scu_command(dev_addr, &cmd_scu);  in set_qam()
8643 		if (rc != 0) {  in set_qam()
8644 			pr_err("error %d\n", rc);  in set_qam()
8649 	rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);  in set_qam()
8650 	if (rc != 0) {  in set_qam()
8651 		pr_err("error %d\n", rc);  in set_qam()
8654 	rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);  in set_qam()
8655 	if (rc != 0) {  in set_qam()
8656 		pr_err("error %d\n", rc);  in set_qam()
8659 	rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);  in set_qam()
8660 	if (rc != 0) {  in set_qam()
8661 		pr_err("error %d\n", rc);  in set_qam()
8667 	return rc;  in set_qam()
8677 	int rc;  in qam_flip_spec()  local
8688 	rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);  in qam_flip_spec()
8689 	if (rc != 0) {  in qam_flip_spec()
8690 		pr_err("error %d\n", rc);  in qam_flip_spec()
8693 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_AC…  in qam_flip_spec()
8694 	if (rc != 0) {  in qam_flip_spec()
8695 		pr_err("error %d\n", rc);  in qam_flip_spec()
8700 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);  in qam_flip_spec()
8701 	if (rc != 0) {  in qam_flip_spec()
8702 		pr_err("error %d\n", rc);  in qam_flip_spec()
8705 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);  in qam_flip_spec()
8706 	if (rc != 0) {  in qam_flip_spec()
8707 		pr_err("error %d\n", rc);  in qam_flip_spec()
8711 	rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);  in qam_flip_spec()
8712 	if (rc != 0) {  in qam_flip_spec()
8713 		pr_err("error %d\n", rc);  in qam_flip_spec()
8716 	rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);  in qam_flip_spec()
8717 	if (rc != 0) {  in qam_flip_spec()
8718 		pr_err("error %d\n", rc);  in qam_flip_spec()
8726 	rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);  in qam_flip_spec()
8727 	if (rc != 0) {  in qam_flip_spec()
8728 		pr_err("error %d\n", rc);  in qam_flip_spec()
8732 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);  in qam_flip_spec()
8733 	if (rc != 0) {  in qam_flip_spec()
8734 		pr_err("error %d\n", rc);  in qam_flip_spec()
8737 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);  in qam_flip_spec()
8738 	if (rc != 0) {  in qam_flip_spec()
8739 		pr_err("error %d\n", rc);  in qam_flip_spec()
8744 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);  in qam_flip_spec()
8745 	if (rc != 0) {  in qam_flip_spec()
8746 		pr_err("error %d\n", rc);  in qam_flip_spec()
8749 	rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);  in qam_flip_spec()
8750 	if (rc != 0) {  in qam_flip_spec()
8751 		pr_err("error %d\n", rc);  in qam_flip_spec()
8754 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);  in qam_flip_spec()
8755 	if (rc != 0) {  in qam_flip_spec()
8756 		pr_err("error %d\n", rc);  in qam_flip_spec()
8761 	rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);  in qam_flip_spec()
8762 	if (rc != 0) {  in qam_flip_spec()
8763 		pr_err("error %d\n", rc);  in qam_flip_spec()
8770 	rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);  in qam_flip_spec()
8771 	if (rc != 0) {  in qam_flip_spec()
8772 		pr_err("error %d\n", rc);  in qam_flip_spec()
8777 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);  in qam_flip_spec()
8778 	if (rc != 0) {  in qam_flip_spec()
8779 		pr_err("error %d\n", rc);  in qam_flip_spec()
8782 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);  in qam_flip_spec()
8783 	if (rc != 0) {  in qam_flip_spec()
8784 		pr_err("error %d\n", rc);  in qam_flip_spec()
8789 		rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);  in qam_flip_spec()
8790 		if (rc != 0) {  in qam_flip_spec()
8791 			pr_err("error %d\n", rc);  in qam_flip_spec()
8794 		rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);  in qam_flip_spec()
8795 		if (rc != 0) {  in qam_flip_spec()
8796 			pr_err("error %d\n", rc);  in qam_flip_spec()
8802 		rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);  in qam_flip_spec()
8803 		if (rc != 0) {  in qam_flip_spec()
8804 			pr_err("error %d\n", rc);  in qam_flip_spec()
8807 		rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);  in qam_flip_spec()
8808 		if (rc != 0) {  in qam_flip_spec()
8809 			pr_err("error %d\n", rc);  in qam_flip_spec()
8815 	rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);  in qam_flip_spec()
8816 	if (rc != 0) {  in qam_flip_spec()
8817 		pr_err("error %d\n", rc);  in qam_flip_spec()
8820 	rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);  in qam_flip_spec()
8821 	if (rc != 0) {  in qam_flip_spec()
8822 		pr_err("error %d\n", rc);  in qam_flip_spec()
8826 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);  in qam_flip_spec()
8827 	if (rc != 0) {  in qam_flip_spec()
8828 		pr_err("error %d\n", rc);  in qam_flip_spec()
8834 		rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);  in qam_flip_spec()
8835 		if (rc != 0) {  in qam_flip_spec()
8836 			pr_err("error %d\n", rc);  in qam_flip_spec()
8840 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);  in qam_flip_spec()
8841 	if (rc != 0) {  in qam_flip_spec()
8842 		pr_err("error %d\n", rc);  in qam_flip_spec()
8848 	return rc;  in qam_flip_spec()
8874 	int rc;  in qam64auto()  local
8886 		rc = ctrl_lock_status(demod, lock_status);  in qam64auto()
8887 		if (rc != 0) {  in qam64auto()
8888 			pr_err("error %d\n", rc);  in qam64auto()
8895 				rc = ctrl_get_qam_sig_quality(demod);  in qam64auto()
8896 				if (rc != 0) {  in qam64auto()
8897 					pr_err("error %d\n", rc);  in qam64auto()
8912 				rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);  in qam64auto()
8913 				if (rc != 0) {  in qam64auto()
8914 					pr_err("error %d\n", rc);  in qam64auto()
8917 				rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);  in qam64auto()
8918 				if (rc != 0) {  in qam64auto()
8919 					pr_err("error %d\n", rc);  in qam64auto()
8930 					rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);  in qam64auto()
8931 					if (rc != 0) {  in qam64auto()
8932 						pr_err("error %d\n", rc);  in qam64auto()
8935 					rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);  in qam64auto()
8936 					if (rc != 0) {  in qam64auto()
8937 						pr_err("error %d\n", rc);  in qam64auto()
8942 					rc = qam_flip_spec(demod, channel);  in qam64auto()
8943 					if (rc != 0) {  in qam64auto()
8944 						pr_err("error %d\n", rc);  in qam64auto()
8964 				rc = ctrl_get_qam_sig_quality(demod);  in qam64auto()
8965 				if (rc != 0) {  in qam64auto()
8966 					pr_err("error %d\n", rc);  in qam64auto()
8970 					rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);  in qam64auto()
8971 					if (rc != 0) {  in qam64auto()
8972 						pr_err("error %d\n", rc);  in qam64auto()
8975 					rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);  in qam64auto()
8976 					if (rc != 0) {  in qam64auto()
8977 						pr_err("error %d\n", rc);  in qam64auto()
9001 	return rc;  in qam64auto()
9022 	int rc;  in qam256auto()  local
9033 		rc = ctrl_lock_status(demod, lock_status);  in qam256auto()
9034 		if (rc != 0) {  in qam256auto()
9035 			pr_err("error %d\n", rc);  in qam256auto()
9041 				rc = ctrl_get_qam_sig_quality(demod);  in qam256auto()
9042 				if (rc != 0) {  in qam256auto()
9043 					pr_err("error %d\n", rc);  in qam256auto()
9059 					rc = qam_flip_spec(demod, channel);  in qam256auto()
9060 					if (rc != 0) {  in qam256auto()
9061 						pr_err("error %d\n", rc);  in qam256auto()
9085 	return rc;  in qam256auto()
9100 	int rc;  in set_qam_channel()  local
9124 		rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);  in set_qam_channel()
9125 		if (rc != 0) {  in set_qam_channel()
9126 			pr_err("error %d\n", rc);  in set_qam_channel()
9131 			rc = qam64auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9134 			rc = qam256auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9136 		if (rc != 0) {  in set_qam_channel()
9137 			pr_err("error %d\n", rc);  in set_qam_channel()
9154 			rc = set_qam(demod, channel, tuner_freq_offset,  in set_qam_channel()
9156 			if (rc != 0) {  in set_qam_channel()
9157 				pr_err("error %d\n", rc);  in set_qam_channel()
9160 			rc = qam256auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9162 			if (rc != 0) {  in set_qam_channel()
9163 				pr_err("error %d\n", rc);  in set_qam_channel()
9180 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9183 			if (rc != 0) {  in set_qam_channel()
9184 				pr_err("error %d\n", rc);  in set_qam_channel()
9187 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9190 			if (rc != 0) {  in set_qam_channel()
9191 				pr_err("error %d\n", rc);  in set_qam_channel()
9194 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9197 			if (rc != 0) {  in set_qam_channel()
9198 				pr_err("error %d\n", rc);  in set_qam_channel()
9202 			rc = set_qam(demod, channel, tuner_freq_offset,  in set_qam_channel()
9204 			if (rc != 0) {  in set_qam_channel()
9205 				pr_err("error %d\n", rc);  in set_qam_channel()
9208 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9211 			if (rc != 0) {  in set_qam_channel()
9212 				pr_err("error %d\n", rc);  in set_qam_channel()
9216 			rc = qam64auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9218 			if (rc != 0) {  in set_qam_channel()
9219 				pr_err("error %d\n", rc);  in set_qam_channel()
9235 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9238 			if (rc != 0) {  in set_qam_channel()
9239 				pr_err("error %d\n", rc);  in set_qam_channel()
9242 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9245 			if (rc != 0) {  in set_qam_channel()
9246 				pr_err("error %d\n", rc);  in set_qam_channel()
9249 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9252 			if (rc != 0) {  in set_qam_channel()
9253 				pr_err("error %d\n", rc);  in set_qam_channel()
9257 			rc = set_qam(demod, channel, tuner_freq_offset,  in set_qam_channel()
9259 			if (rc != 0) {  in set_qam_channel()
9260 				pr_err("error %d\n", rc);  in set_qam_channel()
9263 			rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,  in set_qam_channel()
9266 			if (rc != 0) {  in set_qam_channel()
9267 				pr_err("error %d\n", rc);  in set_qam_channel()
9270 			rc = qam64auto(demod, channel, tuner_freq_offset,  in set_qam_channel()
9272 			if (rc != 0) {  in set_qam_channel()
9273 				pr_err("error %d\n", rc);  in set_qam_channel()
9290 	return rc;  in set_qam_channel()
9307 	int rc;  in get_qamrs_err_count()  local
9319 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);  in get_qamrs_err_count()
9320 	if (rc != 0) {  in get_qamrs_err_count()
9321 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9325 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);  in get_qamrs_err_count()
9326 	if (rc != 0) {  in get_qamrs_err_count()
9327 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9331 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);  in get_qamrs_err_count()
9332 	if (rc != 0) {  in get_qamrs_err_count()
9333 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9337 	rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);  in get_qamrs_err_count()
9338 	if (rc != 0) {  in get_qamrs_err_count()
9339 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9343 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);  in get_qamrs_err_count()
9344 	if (rc != 0) {  in get_qamrs_err_count()
9345 		pr_err("error %d\n", rc);  in get_qamrs_err_count()
9361 	return rc;  in get_qamrs_err_count()
9384 	int rc;  in get_sig_strength()  local
9392 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);  in get_sig_strength()
9393 	if (rc != 0) {  in get_sig_strength()
9394 		pr_err("error %d\n", rc);  in get_sig_strength()
9398 	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);  in get_sig_strength()
9399 	if (rc != 0) {  in get_sig_strength()
9400 		pr_err("error %d\n", rc);  in get_sig_strength()
9443 	return rc;  in get_sig_strength()
9467 	int rc;  in ctrl_get_qam_sig_quality()  local
9497 	rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);  in ctrl_get_qam_sig_quality()
9498 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9499 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9503 	rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);  in ctrl_get_qam_sig_quality()
9504 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9505 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9509 	rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);  in ctrl_get_qam_sig_quality()
9510 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9511 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9562 	rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);  in ctrl_get_qam_sig_quality()
9563 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9564 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9645 	rc = get_acc_pkt_err(demod, &sig_quality->packet_error);  in ctrl_get_qam_sig_quality()
9646 	if (rc != 0) {  in ctrl_get_qam_sig_quality()
9647 		pr_err("error %d\n", rc);  in ctrl_get_qam_sig_quality()
9661 	return rc;  in ctrl_get_qam_sig_quality()
9753 	int rc;  in power_down_atv()  local
9765 	rc = scu_command(dev_addr, &cmd_scu);  in power_down_atv()
9766 	if (rc != 0) {  in power_down_atv()
9767 		pr_err("error %d\n", rc);  in power_down_atv()
9771 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP…  in power_down_atv()
9772 	if (rc != 0) {  in power_down_atv()
9773 		pr_err("error %d\n", rc);  in power_down_atv()
9777 	rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);  in power_down_atv()
9778 	if (rc != 0) {  in power_down_atv()
9779 		pr_err("error %d\n", rc);  in power_down_atv()
9783 		rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);  in power_down_atv()
9784 		if (rc != 0) {  in power_down_atv()
9785 			pr_err("error %d\n", rc);  in power_down_atv()
9788 		rc = set_iqm_af(demod, false);  in power_down_atv()
9789 		if (rc != 0) {  in power_down_atv()
9790 			pr_err("error %d\n", rc);  in power_down_atv()
9794 		rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);  in power_down_atv()
9795 		if (rc != 0) {  in power_down_atv()
9796 			pr_err("error %d\n", rc);  in power_down_atv()
9799 		rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);  in power_down_atv()
9800 		if (rc != 0) {  in power_down_atv()
9801 			pr_err("error %d\n", rc);  in power_down_atv()
9804 		rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);  in power_down_atv()
9805 		if (rc != 0) {  in power_down_atv()
9806 			pr_err("error %d\n", rc);  in power_down_atv()
9809 		rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);  in power_down_atv()
9810 		if (rc != 0) {  in power_down_atv()
9811 			pr_err("error %d\n", rc);  in power_down_atv()
9814 		rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);  in power_down_atv()
9815 		if (rc != 0) {  in power_down_atv()
9816 			pr_err("error %d\n", rc);  in power_down_atv()
9820 	rc = power_down_aud(demod);  in power_down_atv()
9821 	if (rc != 0) {  in power_down_atv()
9822 		pr_err("error %d\n", rc);  in power_down_atv()
9828 	return rc;  in power_down_atv()
9843 	int rc;  in power_down_aud()  local
9848 	rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);  in power_down_aud()
9849 	if (rc != 0) {  in power_down_aud()
9850 		pr_err("error %d\n", rc);  in power_down_aud()
9858 	return rc;  in power_down_aud()
9871 	int rc;  in set_orx_nsu_aox()  local
9875 	rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);  in set_orx_nsu_aox()
9876 	if (rc != 0) {  in set_orx_nsu_aox()
9877 		pr_err("error %d\n", rc);  in set_orx_nsu_aox()
9884 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);  in set_orx_nsu_aox()
9885 	if (rc != 0) {  in set_orx_nsu_aox()
9886 		pr_err("error %d\n", rc);  in set_orx_nsu_aox()
9892 	return rc;  in set_orx_nsu_aox()
9921 	int rc;  in ctrl_set_oob()  local
9958 		rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
9959 		if (rc != 0) {  in ctrl_set_oob()
9960 			pr_err("error %d\n", rc);  in ctrl_set_oob()
9963 		rc = set_orx_nsu_aox(demod, false);  in ctrl_set_oob()
9964 		if (rc != 0) {  in ctrl_set_oob()
9965 			pr_err("error %d\n", rc);  in ctrl_set_oob()
9968 		rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);  in ctrl_set_oob()
9969 		if (rc != 0) {  in ctrl_set_oob()
9970 			pr_err("error %d\n", rc);  in ctrl_set_oob()
10000 	rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);  in ctrl_set_oob()
10001 	if (rc != 0) {  in ctrl_set_oob()
10002 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10010 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
10011 	if (rc != 0) {  in ctrl_set_oob()
10012 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10023 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
10024 	if (rc != 0) {  in ctrl_set_oob()
10025 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10099 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
10100 	if (rc != 0) {  in ctrl_set_oob()
10101 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10105 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);  in ctrl_set_oob()
10106 	if (rc != 0) {  in ctrl_set_oob()
10107 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10110 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_…  in ctrl_set_oob()
10111 	if (rc != 0) {  in ctrl_set_oob()
10112 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10115 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_…  in ctrl_set_oob()
10116 	if (rc != 0) {  in ctrl_set_oob()
10117 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10120 	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);  in ctrl_set_oob()
10121 	if (rc != 0) {  in ctrl_set_oob()
10122 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10126 	rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);  in ctrl_set_oob()
10127 	if (rc != 0) {  in ctrl_set_oob()
10128 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10131 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);  in ctrl_set_oob()
10132 	if (rc != 0) {  in ctrl_set_oob()
10133 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10136 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);  in ctrl_set_oob()
10137 	if (rc != 0) {  in ctrl_set_oob()
10138 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10143 	rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);  in ctrl_set_oob()
10144 	if (rc != 0) {  in ctrl_set_oob()
10145 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10150 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);  in ctrl_set_oob()
10151 	if (rc != 0) {  in ctrl_set_oob()
10152 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10157 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_S…  in ctrl_set_oob()
10158 	if (rc != 0) {  in ctrl_set_oob()
10159 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10162 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048…  in ctrl_set_oob()
10163 	if (rc != 0) {  in ctrl_set_oob()
10164 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10169 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);  in ctrl_set_oob()
10170 	if (rc != 0) {  in ctrl_set_oob()
10171 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10174 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);  in ctrl_set_oob()
10175 	if (rc != 0) {  in ctrl_set_oob()
10176 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10179 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);  in ctrl_set_oob()
10180 	if (rc != 0) {  in ctrl_set_oob()
10181 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10184 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);  in ctrl_set_oob()
10185 	if (rc != 0) {  in ctrl_set_oob()
10186 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10191 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);  in ctrl_set_oob()
10192 	if (rc != 0) {  in ctrl_set_oob()
10193 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10196 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10197 	if (rc != 0) {  in ctrl_set_oob()
10198 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10201 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10202 	if (rc != 0) {  in ctrl_set_oob()
10203 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10206 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10207 	if (rc != 0) {  in ctrl_set_oob()
10208 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10211 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);  in ctrl_set_oob()
10212 	if (rc != 0) {  in ctrl_set_oob()
10213 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10218 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);  in ctrl_set_oob()
10219 	if (rc != 0) {  in ctrl_set_oob()
10220 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10223 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10224 	if (rc != 0) {  in ctrl_set_oob()
10225 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10228 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10229 	if (rc != 0) {  in ctrl_set_oob()
10230 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10233 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10234 	if (rc != 0) {  in ctrl_set_oob()
10235 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10238 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);  in ctrl_set_oob()
10239 	if (rc != 0) {  in ctrl_set_oob()
10240 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10245 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);  in ctrl_set_oob()
10246 	if (rc != 0) {  in ctrl_set_oob()
10247 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10250 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10251 	if (rc != 0) {  in ctrl_set_oob()
10252 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10255 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10256 	if (rc != 0) {  in ctrl_set_oob()
10257 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10260 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10261 	if (rc != 0) {  in ctrl_set_oob()
10262 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10265 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);  in ctrl_set_oob()
10266 	if (rc != 0) {  in ctrl_set_oob()
10267 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10272 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);  in ctrl_set_oob()
10273 	if (rc != 0) {  in ctrl_set_oob()
10274 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10277 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10278 	if (rc != 0) {  in ctrl_set_oob()
10279 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10282 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10283 	if (rc != 0) {  in ctrl_set_oob()
10284 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10287 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10288 	if (rc != 0) {  in ctrl_set_oob()
10289 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10292 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);  in ctrl_set_oob()
10293 	if (rc != 0) {  in ctrl_set_oob()
10294 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10299 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);  in ctrl_set_oob()
10300 	if (rc != 0) {  in ctrl_set_oob()
10301 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10304 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10305 	if (rc != 0) {  in ctrl_set_oob()
10306 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10309 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);  in ctrl_set_oob()
10310 	if (rc != 0) {  in ctrl_set_oob()
10311 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10314 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);  in ctrl_set_oob()
10315 	if (rc != 0) {  in ctrl_set_oob()
10316 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10319 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);  in ctrl_set_oob()
10320 	if (rc != 0) {  in ctrl_set_oob()
10321 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10326 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);  in ctrl_set_oob()
10327 	if (rc != 0) {  in ctrl_set_oob()
10328 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10331 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);  in ctrl_set_oob()
10332 	if (rc != 0) {  in ctrl_set_oob()
10333 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10336 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);  in ctrl_set_oob()
10337 	if (rc != 0) {  in ctrl_set_oob()
10338 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10341 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);  in ctrl_set_oob()
10342 	if (rc != 0) {  in ctrl_set_oob()
10343 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10346 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);  in ctrl_set_oob()
10347 	if (rc != 0) {  in ctrl_set_oob()
10348 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10353 …rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)…  in ctrl_set_oob()
10354 	if (rc != 0) {  in ctrl_set_oob()
10355 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10358 	rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);  in ctrl_set_oob()
10359 	if (rc != 0) {  in ctrl_set_oob()
10360 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10366 		rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);  in ctrl_set_oob()
10367 		if (rc != 0) {  in ctrl_set_oob()
10368 			pr_err("error %d\n", rc);  in ctrl_set_oob()
10371 		rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);  in ctrl_set_oob()
10372 		if (rc != 0) {  in ctrl_set_oob()
10373 			pr_err("error %d\n", rc);  in ctrl_set_oob()
10377 	rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);  in ctrl_set_oob()
10378 	if (rc != 0) {  in ctrl_set_oob()
10379 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10382 	rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);  in ctrl_set_oob()
10383 	if (rc != 0) {  in ctrl_set_oob()
10384 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10395 	rc = scu_command(dev_addr, &scu_cmd);  in ctrl_set_oob()
10396 	if (rc != 0) {  in ctrl_set_oob()
10397 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10401 	rc = set_orx_nsu_aox(demod, true);  in ctrl_set_oob()
10402 	if (rc != 0) {  in ctrl_set_oob()
10403 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10406 	rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);  in ctrl_set_oob()
10407 	if (rc != 0) {  in ctrl_set_oob()
10408 		pr_err("error %d\n", rc);  in ctrl_set_oob()
10416 	return rc;  in ctrl_set_oob()
10444 	int rc;  in ctrl_set_channel()  local
10507 		rc = ctrl_set_uio_cfg(demod, &uio_cfg);  in ctrl_set_channel()
10508 		if (rc != 0) {  in ctrl_set_channel()
10509 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10602 		rc = ctrl_uio_write(demod, &uio1);  in ctrl_set_channel()
10603 		if (rc != 0) {  in ctrl_set_channel()
10604 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10609 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);  in ctrl_set_channel()
10610 	if (rc != 0) {  in ctrl_set_channel()
10611 		pr_err("error %d\n", rc);  in ctrl_set_channel()
10624 		rc = set_vsb(demod);  in ctrl_set_channel()
10625 		if (rc != 0) {  in ctrl_set_channel()
10626 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10629 		rc = set_frequency(demod, channel, tuner_freq_offset);  in ctrl_set_channel()
10630 		if (rc != 0) {  in ctrl_set_channel()
10631 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10639 		rc = set_qam_channel(demod, channel, tuner_freq_offset);  in ctrl_set_channel()
10640 		if (rc != 0) {  in ctrl_set_channel()
10641 			pr_err("error %d\n", rc);  in ctrl_set_channel()
10656 	return rc;  in ctrl_set_channel()
10683 	int rc;  in ctrl_sig_quality()  local
10687 	rc = get_sig_strength(demod, &strength);  in ctrl_sig_quality()
10688 	if (rc < 0) {  in ctrl_sig_quality()
10689 		pr_err("error getting signal strength %d\n", rc);  in ctrl_sig_quality()
10699 		rc = get_acc_pkt_err(demod, &pkt);  in ctrl_sig_quality()
10700 		if (rc != 0) {  in ctrl_sig_quality()
10701 			pr_err("error %d\n", rc);  in ctrl_sig_quality()
10714 			rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);  in ctrl_sig_quality()
10715 			if (rc != 0) {  in ctrl_sig_quality()
10716 				pr_err("error %d getting UCB\n", rc);  in ctrl_sig_quality()
10726 			rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);  in ctrl_sig_quality()
10727 			if (rc != 0) {  in ctrl_sig_quality()
10728 				pr_err("error %d getting pre-ber\n", rc);  in ctrl_sig_quality()
10737 			rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);  in ctrl_sig_quality()
10738 			if (rc != 0) {  in ctrl_sig_quality()
10739 				pr_err("error %d getting post-ber\n", rc);  in ctrl_sig_quality()
10747 			rc = get_vsbmer(dev_addr, &mer);  in ctrl_sig_quality()
10748 			if (rc != 0) {  in ctrl_sig_quality()
10749 				pr_err("error %d getting MER\n", rc);  in ctrl_sig_quality()
10761 		rc = ctrl_get_qam_sig_quality(demod);  in ctrl_sig_quality()
10762 		if (rc != 0) {  in ctrl_sig_quality()
10763 			pr_err("error %d\n", rc);  in ctrl_sig_quality()
10774 	return rc;  in ctrl_sig_quality()
10799 	int rc;  in ctrl_lock_status()  local
10838 	rc = scu_command(dev_addr, &cmd_scu);  in ctrl_lock_status()
10839 	if (rc != 0) {  in ctrl_lock_status()
10840 		pr_err("error %d\n", rc);  in ctrl_lock_status()
10862 	return rc;  in ctrl_lock_status()
10881 	int rc;  in ctrl_set_standard()  local
10899 		rc = power_down_qam(demod, false);  in ctrl_set_standard()
10900 		if (rc != 0) {  in ctrl_set_standard()
10901 			pr_err("error %d\n", rc);  in ctrl_set_standard()
10907 		rc = power_down_vsb(demod, false);  in ctrl_set_standard()
10908 		if (rc != 0) {  in ctrl_set_standard()
10909 			pr_err("error %d\n", rc);  in ctrl_set_standard()
10934 			rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);  in ctrl_set_standard()
10935 			if (rc != 0) {  in ctrl_set_standard()
10936 				pr_err("error %d\n", rc);  in ctrl_set_standard()
10943 		rc = set_vsb_leak_n_gain(demod);  in ctrl_set_standard()
10944 		if (rc != 0) {  in ctrl_set_standard()
10945 			pr_err("error %d\n", rc);  in ctrl_set_standard()
10958 	return rc;  in ctrl_set_standard()
11040 	int rc;  in ctrl_power_mode()  local
11076 		rc = power_up_device(demod);  in ctrl_power_mode()
11077 		if (rc != 0) {  in ctrl_power_mode()
11078 			pr_err("error %d\n", rc);  in ctrl_power_mode()
11104 			rc = power_down_qam(demod, true);  in ctrl_power_mode()
11105 			if (rc != 0) {  in ctrl_power_mode()
11106 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11111 			rc = power_down_vsb(demod, true);  in ctrl_power_mode()
11112 			if (rc != 0) {  in ctrl_power_mode()
11113 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11124 			rc = power_down_atv(demod, ext_attr->standard, true);  in ctrl_power_mode()
11125 			if (rc != 0) {  in ctrl_power_mode()
11126 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11141 		rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);  in ctrl_power_mode()
11142 		if (rc != 0) {  in ctrl_power_mode()
11143 			pr_err("error %d\n", rc);  in ctrl_power_mode()
11146 		rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);  in ctrl_power_mode()
11147 		if (rc != 0) {  in ctrl_power_mode()
11148 			pr_err("error %d\n", rc);  in ctrl_power_mode()
11154 			rc = init_hi(demod);  in ctrl_power_mode()
11155 			if (rc != 0) {  in ctrl_power_mode()
11156 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11161 			rc = hi_cfg_command(demod);  in ctrl_power_mode()
11162 			if (rc != 0) {  in ctrl_power_mode()
11163 				pr_err("error %d\n", rc);  in ctrl_power_mode()
11173 	return rc;  in ctrl_power_mode()
11196 	int rc;  in ctrl_set_cfg_pre_saw()  local
11213 		rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);  in ctrl_set_cfg_pre_saw()
11214 		if (rc != 0) {  in ctrl_set_cfg_pre_saw()
11215 			pr_err("error %d\n", rc);  in ctrl_set_cfg_pre_saw()
11238 	return rc;  in ctrl_set_cfg_pre_saw()
11259 	int rc;  in ctrl_set_cfg_afe_gain()  local
11294 			rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);  in ctrl_set_cfg_afe_gain()
11295 			if (rc != 0) {  in ctrl_set_cfg_afe_gain()
11296 				pr_err("error %d\n", rc);  in ctrl_set_cfg_afe_gain()
11319 	return rc;  in ctrl_set_cfg_afe_gain()
11352 	int rc;  in drxj_open()  local
11371 	rc = ctrl_power_mode(demod, &power_mode);  in drxj_open()
11372 	if (rc != 0) {  in drxj_open()
11373 		pr_err("error %d\n", rc);  in drxj_open()
11377 		rc = -EINVAL;  in drxj_open()
11383 	rc = get_device_capabilities(demod);  in drxj_open()
11384 	if (rc != 0) {  in drxj_open()
11385 		pr_err("error %d\n", rc);  in drxj_open()
11397 …rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SO…  in drxj_open()
11398 	if (rc != 0) {  in drxj_open()
11399 		pr_err("error %d\n", rc);  in drxj_open()
11402 	rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);  in drxj_open()
11403 	if (rc != 0) {  in drxj_open()
11404 		pr_err("error %d\n", rc);  in drxj_open()
11411 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_…  in drxj_open()
11412 	if (rc != 0) {  in drxj_open()
11413 		pr_err("error %d\n", rc);  in drxj_open()
11417 	rc = set_iqm_af(demod, false);  in drxj_open()
11418 	if (rc != 0) {  in drxj_open()
11419 		pr_err("error %d\n", rc);  in drxj_open()
11422 	rc = set_orx_nsu_aox(demod, false);  in drxj_open()
11423 	if (rc != 0) {  in drxj_open()
11424 		pr_err("error %d\n", rc);  in drxj_open()
11428 	rc = init_hi(demod);  in drxj_open()
11429 	if (rc != 0) {  in drxj_open()
11430 		pr_err("error %d\n", rc);  in drxj_open()
11438 	rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);  in drxj_open()
11439 	if (rc != 0) {  in drxj_open()
11440 		pr_err("error %d\n", rc);  in drxj_open()
11444 	rc = power_down_aud(demod);  in drxj_open()
11445 	if (rc != 0) {  in drxj_open()
11446 		pr_err("error %d\n", rc);  in drxj_open()
11450 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);  in drxj_open()
11451 	if (rc != 0) {  in drxj_open()
11452 		pr_err("error %d\n", rc);  in drxj_open()
11468 		rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);  in drxj_open()
11469 		if (rc != 0) {  in drxj_open()
11470 			pr_err("error %d while uploading the firmware\n", rc);  in drxj_open()
11474 			rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);  in drxj_open()
11475 			if (rc != 0) {  in drxj_open()
11477 				       rc);  in drxj_open()
11485 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);  in drxj_open()
11486 	if (rc != 0) {  in drxj_open()
11487 		pr_err("error %d\n", rc);  in drxj_open()
11498 	rc = smart_ant_init(demod);  in drxj_open()
11499 	if (rc != 0) {  in drxj_open()
11500 		pr_err("error %d\n", rc);  in drxj_open()
11523 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);  in drxj_open()
11524 	if (rc != 0) {  in drxj_open()
11525 		pr_err("error %d\n", rc);  in drxj_open()
11528 	rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);  in drxj_open()
11529 	if (rc != 0) {  in drxj_open()
11530 		pr_err("error %d\n", rc);  in drxj_open()
11534 	rc = ctrl_set_oob(demod, NULL);  in drxj_open()
11535 	if (rc != 0) {  in drxj_open()
11536 		pr_err("error %d\n", rc);  in drxj_open()
11548 	return rc;  in drxj_open()
11561 	int rc;  in drxj_close()  local
11572 	rc = ctrl_power_mode(demod, &power_mode);  in drxj_close()
11573 	if (rc != 0) {  in drxj_close()
11574 		pr_err("error %d\n", rc);  in drxj_close()
11578 	rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);  in drxj_close()
11579 	if (rc != 0) {  in drxj_close()
11580 		pr_err("error %d\n", rc);  in drxj_close()
11584 	rc = ctrl_power_mode(demod, &power_mode);  in drxj_close()
11585 	if (rc != 0) {  in drxj_close()
11586 		pr_err("error %d\n", rc);  in drxj_close()
11596 	return rc;  in drxj_close()
11741 	int rc;  in drx_ctrl_u_code()  local
11759 		rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent);  in drx_ctrl_u_code()
11760 		if (rc < 0) {  in drx_ctrl_u_code()
11762 			return rc;  in drx_ctrl_u_code()
11767 			rc = -EINVAL;  in drx_ctrl_u_code()
11787 		rc = -EINVAL;  in drx_ctrl_u_code()
11793 		rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);  in drx_ctrl_u_code()
11794 		if (rc)  in drx_ctrl_u_code()
11829 			rc = -EINVAL;  in drx_ctrl_u_code()
11846 				rc = -EIO;  in drx_ctrl_u_code()
11904 	return rc;  in drx_ctrl_u_code()
12219 	int rc = 0;  in drx39xxj_init()  local
12224 		rc = drxj_open(demod);  in drx39xxj_init()
12225 		if (rc != 0)  in drx39xxj_init()
12226 			pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);  in drx39xxj_init()
12230 	return rc;  in drx39xxj_init()