23 #define REG_CR		0x00  macro
149 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_write()
151 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
153 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_write()
155 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
170 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_write()
172 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
196 			writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_write()
202 				writew(CR_ENABLE, i2c_dev->base + REG_CR);  in wmt_i2c_write()
206 			writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);  in wmt_i2c_write()
228 	val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
230 	writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
232 	val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
234 	writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
237 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
239 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
243 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
245 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
260 		val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
262 		writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
280 			val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
282 			writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
284 			val = readw(i2c_dev->base + REG_CR);  in wmt_i2c_read()
286 			writew(val, i2c_dev->base + REG_CR);  in wmt_i2c_read()
354 	writew(0, i2c_dev->base + REG_CR);  in wmt_i2c_reset_hardware()
358 	writew(CR_ENABLE, i2c_dev->base + REG_CR);  in wmt_i2c_reset_hardware()