Lines Matching refs:priv
95 static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_clr_pend_irq() argument
97 u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); in hix5hd2_i2c_clr_pend_irq()
99 writel_relaxed(val, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_pend_irq()
104 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_clr_all_irq() argument
106 writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR); in hix5hd2_i2c_clr_all_irq()
109 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_disable_irq() argument
111 writel_relaxed(0, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_disable_irq()
114 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_enable_irq() argument
117 priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_enable_irq()
120 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_drv_setrate() argument
126 val = readl_relaxed(priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
127 writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
129 rate = priv->freq; in hix5hd2_i2c_drv_setrate()
130 sysclock = clk_get_rate(priv->clk); in hix5hd2_i2c_drv_setrate()
132 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H); in hix5hd2_i2c_drv_setrate()
133 writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L); in hix5hd2_i2c_drv_setrate()
136 writel_relaxed(val, priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
138 dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n", in hix5hd2_i2c_drv_setrate()
142 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_init() argument
144 hix5hd2_i2c_disable_irq(priv); in hix5hd2_i2c_init()
145 hix5hd2_i2c_drv_setrate(priv); in hix5hd2_i2c_init()
146 hix5hd2_i2c_clr_all_irq(priv); in hix5hd2_i2c_init()
147 hix5hd2_i2c_enable_irq(priv); in hix5hd2_i2c_init()
150 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_reset() argument
152 clk_disable_unprepare(priv->clk); in hix5hd2_i2c_reset()
154 clk_prepare_enable(priv->clk); in hix5hd2_i2c_reset()
155 hix5hd2_i2c_init(priv); in hix5hd2_i2c_reset()
158 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv) in hix5hd2_i2c_wait_bus_idle() argument
166 int_status = hix5hd2_i2c_clr_pend_irq(priv); in hix5hd2_i2c_wait_bus_idle()
176 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv) in hix5hd2_rw_over() argument
178 if (priv->state == HIX5I2C_STAT_SND_STOP) in hix5hd2_rw_over()
179 dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__); in hix5hd2_rw_over()
181 dev_dbg(priv->dev, "%s: have not data to send\n", __func__); in hix5hd2_rw_over()
183 priv->state = HIX5I2C_STAT_RW_SUCCESS; in hix5hd2_rw_over()
184 priv->err = 0; in hix5hd2_rw_over()
187 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv) in hix5hd2_rw_handle_stop() argument
189 if (priv->stop) { in hix5hd2_rw_handle_stop()
190 priv->state = HIX5I2C_STAT_SND_STOP; in hix5hd2_rw_handle_stop()
191 writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM); in hix5hd2_rw_handle_stop()
193 hix5hd2_rw_over(priv); in hix5hd2_rw_handle_stop()
197 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv) in hix5hd2_read_handle() argument
199 if (priv->msg_len == 1) { in hix5hd2_read_handle()
201 writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM); in hix5hd2_read_handle()
202 } else if (priv->msg_len > 1) { in hix5hd2_read_handle()
204 writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM); in hix5hd2_read_handle()
206 hix5hd2_rw_handle_stop(priv); in hix5hd2_read_handle()
210 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv) in hix5hd2_write_handle() argument
214 if (priv->msg_len > 0) { in hix5hd2_write_handle()
215 data = priv->msg->buf[priv->msg_idx++]; in hix5hd2_write_handle()
216 writel_relaxed(data, priv->regs + HIX5I2C_TXR); in hix5hd2_write_handle()
217 writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM); in hix5hd2_write_handle()
219 hix5hd2_rw_handle_stop(priv); in hix5hd2_write_handle()
223 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv) in hix5hd2_rw_preprocess() argument
227 if (priv->state == HIX5I2C_STAT_INIT) { in hix5hd2_rw_preprocess()
228 priv->state = HIX5I2C_STAT_RW; in hix5hd2_rw_preprocess()
229 } else if (priv->state == HIX5I2C_STAT_RW) { in hix5hd2_rw_preprocess()
230 if (priv->msg->flags & I2C_M_RD) { in hix5hd2_rw_preprocess()
231 data = readl_relaxed(priv->regs + HIX5I2C_RXR); in hix5hd2_rw_preprocess()
232 priv->msg->buf[priv->msg_idx++] = data; in hix5hd2_rw_preprocess()
234 priv->msg_len--; in hix5hd2_rw_preprocess()
236 dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n", in hix5hd2_rw_preprocess()
237 __func__, priv->state, priv->msg_len); in hix5hd2_rw_preprocess()
245 struct hix5hd2_i2c_priv *priv = dev_id; in hix5hd2_i2c_irq() local
249 spin_lock(&priv->lock); in hix5hd2_i2c_irq()
251 int_status = hix5hd2_i2c_clr_pend_irq(priv); in hix5hd2_i2c_irq()
256 dev_dbg(priv->dev, "ARB bus loss\n"); in hix5hd2_i2c_irq()
257 priv->err = -EAGAIN; in hix5hd2_i2c_irq()
258 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_irq()
262 dev_dbg(priv->dev, "No ACK from device\n"); in hix5hd2_i2c_irq()
263 priv->err = -ENXIO; in hix5hd2_i2c_irq()
264 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_irq()
269 if (priv->msg_len > 0) { in hix5hd2_i2c_irq()
270 ret = hix5hd2_rw_preprocess(priv); in hix5hd2_i2c_irq()
272 priv->err = ret; in hix5hd2_i2c_irq()
273 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_irq()
276 if (priv->msg->flags & I2C_M_RD) in hix5hd2_i2c_irq()
277 hix5hd2_read_handle(priv); in hix5hd2_i2c_irq()
279 hix5hd2_write_handle(priv); in hix5hd2_i2c_irq()
281 hix5hd2_rw_over(priv); in hix5hd2_i2c_irq()
286 if ((priv->state == HIX5I2C_STAT_RW_SUCCESS && in hix5hd2_i2c_irq()
287 priv->msg->len == priv->msg_idx) || in hix5hd2_i2c_irq()
288 (priv->state == HIX5I2C_STAT_RW_ERR)) { in hix5hd2_i2c_irq()
289 hix5hd2_i2c_disable_irq(priv); in hix5hd2_i2c_irq()
290 hix5hd2_i2c_clr_pend_irq(priv); in hix5hd2_i2c_irq()
291 complete(&priv->msg_complete); in hix5hd2_i2c_irq()
294 spin_unlock(&priv->lock); in hix5hd2_i2c_irq()
299 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop) in hix5hd2_i2c_message_start() argument
303 spin_lock_irqsave(&priv->lock, flags); in hix5hd2_i2c_message_start()
304 hix5hd2_i2c_clr_all_irq(priv); in hix5hd2_i2c_message_start()
305 hix5hd2_i2c_enable_irq(priv); in hix5hd2_i2c_message_start()
307 writel_relaxed(i2c_8bit_addr_from_msg(priv->msg), in hix5hd2_i2c_message_start()
308 priv->regs + HIX5I2C_TXR); in hix5hd2_i2c_message_start()
310 writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM); in hix5hd2_i2c_message_start()
311 spin_unlock_irqrestore(&priv->lock, flags); in hix5hd2_i2c_message_start()
314 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv, in hix5hd2_i2c_xfer_msg() argument
320 priv->msg = msgs; in hix5hd2_i2c_xfer_msg()
321 priv->msg_idx = 0; in hix5hd2_i2c_xfer_msg()
322 priv->msg_len = priv->msg->len; in hix5hd2_i2c_xfer_msg()
323 priv->stop = stop; in hix5hd2_i2c_xfer_msg()
324 priv->err = 0; in hix5hd2_i2c_xfer_msg()
325 priv->state = HIX5I2C_STAT_INIT; in hix5hd2_i2c_xfer_msg()
327 reinit_completion(&priv->msg_complete); in hix5hd2_i2c_xfer_msg()
328 hix5hd2_i2c_message_start(priv, stop); in hix5hd2_i2c_xfer_msg()
330 timeout = wait_for_completion_timeout(&priv->msg_complete, in hix5hd2_i2c_xfer_msg()
331 priv->adap.timeout); in hix5hd2_i2c_xfer_msg()
333 priv->state = HIX5I2C_STAT_RW_ERR; in hix5hd2_i2c_xfer_msg()
334 priv->err = -ETIMEDOUT; in hix5hd2_i2c_xfer_msg()
335 dev_warn(priv->dev, "%s timeout=%d\n", in hix5hd2_i2c_xfer_msg()
337 priv->adap.timeout); in hix5hd2_i2c_xfer_msg()
339 ret = priv->state; in hix5hd2_i2c_xfer_msg()
345 if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop) in hix5hd2_i2c_xfer_msg()
346 ret = hix5hd2_i2c_wait_bus_idle(priv); in hix5hd2_i2c_xfer_msg()
349 hix5hd2_i2c_reset(priv); in hix5hd2_i2c_xfer_msg()
351 return priv->err; in hix5hd2_i2c_xfer_msg()
357 struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap); in hix5hd2_i2c_xfer() local
360 pm_runtime_get_sync(priv->dev); in hix5hd2_i2c_xfer()
364 ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop); in hix5hd2_i2c_xfer()
372 pm_runtime_mark_last_busy(priv->dev); in hix5hd2_i2c_xfer()
373 pm_runtime_put_autosuspend(priv->dev); in hix5hd2_i2c_xfer()
390 struct hix5hd2_i2c_priv *priv; in hix5hd2_i2c_probe() local
394 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in hix5hd2_i2c_probe()
395 if (!priv) in hix5hd2_i2c_probe()
400 priv->freq = I2C_MAX_STANDARD_MODE_FREQ; in hix5hd2_i2c_probe()
403 priv->freq = I2C_MAX_FAST_MODE_FREQ; in hix5hd2_i2c_probe()
404 dev_warn(priv->dev, "use max freq %d instead\n", in hix5hd2_i2c_probe()
407 priv->freq = freq; in hix5hd2_i2c_probe()
411 priv->regs = devm_platform_ioremap_resource(pdev, 0); in hix5hd2_i2c_probe()
412 if (IS_ERR(priv->regs)) in hix5hd2_i2c_probe()
413 return PTR_ERR(priv->regs); in hix5hd2_i2c_probe()
419 priv->clk = devm_clk_get(&pdev->dev, NULL); in hix5hd2_i2c_probe()
420 if (IS_ERR(priv->clk)) { in hix5hd2_i2c_probe()
422 return PTR_ERR(priv->clk); in hix5hd2_i2c_probe()
424 clk_prepare_enable(priv->clk); in hix5hd2_i2c_probe()
426 strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name)); in hix5hd2_i2c_probe()
427 priv->dev = &pdev->dev; in hix5hd2_i2c_probe()
428 priv->adap.owner = THIS_MODULE; in hix5hd2_i2c_probe()
429 priv->adap.algo = &hix5hd2_i2c_algorithm; in hix5hd2_i2c_probe()
430 priv->adap.retries = 3; in hix5hd2_i2c_probe()
431 priv->adap.dev.of_node = np; in hix5hd2_i2c_probe()
432 priv->adap.algo_data = priv; in hix5hd2_i2c_probe()
433 priv->adap.dev.parent = &pdev->dev; in hix5hd2_i2c_probe()
434 i2c_set_adapdata(&priv->adap, priv); in hix5hd2_i2c_probe()
435 platform_set_drvdata(pdev, priv); in hix5hd2_i2c_probe()
436 spin_lock_init(&priv->lock); in hix5hd2_i2c_probe()
437 init_completion(&priv->msg_complete); in hix5hd2_i2c_probe()
439 hix5hd2_i2c_init(priv); in hix5hd2_i2c_probe()
442 IRQF_NO_SUSPEND, dev_name(&pdev->dev), priv); in hix5hd2_i2c_probe()
448 pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC); in hix5hd2_i2c_probe()
449 pm_runtime_use_autosuspend(priv->dev); in hix5hd2_i2c_probe()
450 pm_runtime_set_active(priv->dev); in hix5hd2_i2c_probe()
451 pm_runtime_enable(priv->dev); in hix5hd2_i2c_probe()
453 ret = i2c_add_adapter(&priv->adap); in hix5hd2_i2c_probe()
460 pm_runtime_disable(priv->dev); in hix5hd2_i2c_probe()
461 pm_runtime_set_suspended(priv->dev); in hix5hd2_i2c_probe()
463 clk_disable_unprepare(priv->clk); in hix5hd2_i2c_probe()
469 struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev); in hix5hd2_i2c_remove() local
471 i2c_del_adapter(&priv->adap); in hix5hd2_i2c_remove()
472 pm_runtime_disable(priv->dev); in hix5hd2_i2c_remove()
473 pm_runtime_set_suspended(priv->dev); in hix5hd2_i2c_remove()
474 clk_disable_unprepare(priv->clk); in hix5hd2_i2c_remove()
482 struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev); in hix5hd2_i2c_runtime_suspend() local
484 clk_disable_unprepare(priv->clk); in hix5hd2_i2c_runtime_suspend()
491 struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev); in hix5hd2_i2c_runtime_resume() local
493 clk_prepare_enable(priv->clk); in hix5hd2_i2c_runtime_resume()
494 hix5hd2_i2c_init(priv); in hix5hd2_i2c_runtime_resume()