141 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_phy_init()
142 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0);  in vc4_hdmi_phy_init()
152 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16);  in vc4_hdmi_phy_disable()
161 	HDMI_WRITE(HDMI_TX_PHY_CTL_0,  in vc4_hdmi_phy_rng_enable()
172 	HDMI_WRITE(HDMI_TX_PHY_CTL_0,  in vc4_hdmi_phy_rng_disable()
359 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0x0f);  in vc5_hdmi_reset_phy()
360 	HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL, BIT(10));  in vc5_hdmi_reset_phy()
380 	HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,  in vc5_hdmi_phy_init()
383 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,  in vc5_hdmi_phy_init()
390 	HDMI_WRITE(HDMI_RM_CONTROL,  in vc5_hdmi_phy_init()
396 	HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,  in vc5_hdmi_phy_init()
401 	HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,  in vc5_hdmi_phy_init()
406 	HDMI_WRITE(HDMI_RM_OFFSET,  in vc5_hdmi_phy_init()
411 	HDMI_WRITE(HDMI_TX_PHY_CLK_DIV,  in vc5_hdmi_phy_init()
414 	HDMI_WRITE(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,  in vc5_hdmi_phy_init()
418 	HDMI_WRITE(HDMI_TX_PHY_PLL_CTL_0,  in vc5_hdmi_phy_init()
424 	HDMI_WRITE(HDMI_TX_PHY_PLL_CTL_1,  in vc5_hdmi_phy_init()
431 	HDMI_WRITE(HDMI_RM_FORMAT,  in vc5_hdmi_phy_init()
435 	HDMI_WRITE(HDMI_TX_PHY_PLL_CFG,  in vc5_hdmi_phy_init()
443 	HDMI_WRITE(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, word_sel);  in vc5_hdmi_phy_init()
445 	HDMI_WRITE(HDMI_TX_PHY_CTL_3,  in vc5_hdmi_phy_init()
467 	HDMI_WRITE(HDMI_TX_PHY_CTL_0,  in vc5_hdmi_phy_init()
485 	HDMI_WRITE(HDMI_TX_PHY_CTL_1,  in vc5_hdmi_phy_init()
496 	HDMI_WRITE(HDMI_TX_PHY_CTL_2,  in vc5_hdmi_phy_init()
508 	HDMI_WRITE(HDMI_TX_PHY_CHANNEL_SWAP,  in vc5_hdmi_phy_init()
518 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,  in vc5_hdmi_phy_init()
523 	HDMI_WRITE(HDMI_TX_PHY_RESET_CTL,  in vc5_hdmi_phy_init()
545 	HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,  in vc5_hdmi_phy_rng_enable()
556 	HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL,  in vc5_hdmi_phy_rng_disable()