18 #define DATA					1  macro
132 		regmap_write(regmap, 0x41, val[DATA]);  in dphy_set_timing_reg()
133 		regmap_write(regmap, 0x51, val[DATA]);  in dphy_set_timing_reg()
134 		regmap_write(regmap, 0x61, val[DATA]);  in dphy_set_timing_reg()
135 		regmap_write(regmap, 0x71, val[DATA]);  in dphy_set_timing_reg()
138 		regmap_write(regmap, 0xa0, val[DATA]);  in dphy_set_timing_reg()
139 		regmap_write(regmap, 0xb0, val[DATA]);  in dphy_set_timing_reg()
140 		regmap_write(regmap, 0xc0, val[DATA]);  in dphy_set_timing_reg()
141 		regmap_write(regmap, 0xd0, val[DATA]);  in dphy_set_timing_reg()
145 		regmap_write(regmap, 0x42, val[DATA]);  in dphy_set_timing_reg()
146 		regmap_write(regmap, 0x52, val[DATA]);  in dphy_set_timing_reg()
147 		regmap_write(regmap, 0x62, val[DATA]);  in dphy_set_timing_reg()
148 		regmap_write(regmap, 0x72, val[DATA]);  in dphy_set_timing_reg()
151 		regmap_write(regmap, 0xa1, val[DATA]);  in dphy_set_timing_reg()
152 		regmap_write(regmap, 0xb1, val[DATA]);  in dphy_set_timing_reg()
153 		regmap_write(regmap, 0xc1, val[DATA]);  in dphy_set_timing_reg()
154 		regmap_write(regmap, 0xd1, val[DATA]);  in dphy_set_timing_reg()
158 		regmap_write(regmap, 0x43, val[DATA]);  in dphy_set_timing_reg()
159 		regmap_write(regmap, 0x53, val[DATA]);  in dphy_set_timing_reg()
160 		regmap_write(regmap, 0x63, val[DATA]);  in dphy_set_timing_reg()
161 		regmap_write(regmap, 0x73, val[DATA]);  in dphy_set_timing_reg()
164 		regmap_write(regmap, 0xa2, val[DATA]);  in dphy_set_timing_reg()
165 		regmap_write(regmap, 0xb2, val[DATA]);  in dphy_set_timing_reg()
166 		regmap_write(regmap, 0xc2, val[DATA]);  in dphy_set_timing_reg()
167 		regmap_write(regmap, 0xd2, val[DATA]);  in dphy_set_timing_reg()
171 		regmap_write(regmap, 0x44, val[DATA]);  in dphy_set_timing_reg()
172 		regmap_write(regmap, 0x54, val[DATA]);  in dphy_set_timing_reg()
173 		regmap_write(regmap, 0x64, val[DATA]);  in dphy_set_timing_reg()
174 		regmap_write(regmap, 0x74, val[DATA]);  in dphy_set_timing_reg()
177 		regmap_write(regmap, 0xa3, val[DATA]);  in dphy_set_timing_reg()
178 		regmap_write(regmap, 0xb3, val[DATA]);  in dphy_set_timing_reg()
179 		regmap_write(regmap, 0xc3, val[DATA]);  in dphy_set_timing_reg()
180 		regmap_write(regmap, 0xd3, val[DATA]);  in dphy_set_timing_reg()
184 		regmap_write(regmap, 0x46, val[DATA]);  in dphy_set_timing_reg()
185 		regmap_write(regmap, 0x56, val[DATA]);  in dphy_set_timing_reg()
186 		regmap_write(regmap, 0x66, val[DATA]);  in dphy_set_timing_reg()
187 		regmap_write(regmap, 0x76, val[DATA]);  in dphy_set_timing_reg()
190 		regmap_write(regmap, 0xA5, val[DATA]);  in dphy_set_timing_reg()
191 		regmap_write(regmap, 0xB5, val[DATA]);  in dphy_set_timing_reg()
192 		regmap_write(regmap, 0xc5, val[DATA]);  in dphy_set_timing_reg()
193 		regmap_write(regmap, 0xd5, val[DATA]);  in dphy_set_timing_reg()
239 	val[DATA] = val[CLK];  in dphy_timing_config()
250 	val[DATA] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1;  in dphy_timing_config()
259 	val[DATA] = DIV_ROUND_UP(range[L] * factor  in dphy_timing_config()
269 	val[DATA] = DIV_ROUND_UP(range[L] * 3 / 2 - constant, t_half_byteck) - 2;  in dphy_timing_config()
276 	val[DATA] = val[CLK];  in dphy_timing_config()
283 	val[DATA] = val[CLK];  in dphy_timing_config()