17 #define CLK						0  macro
131 		regmap_write(regmap, 0x31, val[CLK]);  in dphy_set_timing_reg()
137 		regmap_write(regmap, 0x90, val[CLK]);  in dphy_set_timing_reg()
144 		regmap_write(regmap, 0x32, val[CLK]);  in dphy_set_timing_reg()
150 		regmap_write(regmap, 0x91, val[CLK]);  in dphy_set_timing_reg()
157 		regmap_write(regmap, 0x33, val[CLK]);  in dphy_set_timing_reg()
163 		regmap_write(regmap, 0x92, val[CLK]);  in dphy_set_timing_reg()
170 		regmap_write(regmap, 0x34, val[CLK]);  in dphy_set_timing_reg()
176 		regmap_write(regmap, 0x93, val[CLK]);  in dphy_set_timing_reg()
183 		regmap_write(regmap, 0x36, val[CLK]);  in dphy_set_timing_reg()
189 		regmap_write(regmap, 0x95, val[CLK]);  in dphy_set_timing_reg()
196 		regmap_write(regmap, 0x35, val[CLK]);  in dphy_set_timing_reg()
197 		regmap_write(regmap, 0x94, val[CLK]);  in dphy_set_timing_reg()
238 	val[CLK] = DIV_ROUND_UP(range[L] * (factor << 1), t_byteck) - 2;  in dphy_timing_config()
239 	val[DATA] = val[CLK];  in dphy_timing_config()
246 	val[CLK] = DIV_ROUND_UP(AVERAGE(range[L], range[H]), t_half_byteck) - 1;  in dphy_timing_config()
256 	val[CLK] = DIV_ROUND_UP(range[L] * factor + (tmp & 0xffff)  in dphy_timing_config()
267 	val[CLK] = DIV_ROUND_UP(range[L] * factor - constant, t_half_byteck);  in dphy_timing_config()
275 	val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;  in dphy_timing_config()
276 	val[DATA] = val[CLK];  in dphy_timing_config()
282 	val[CLK] = DIV_ROUND_UP(range[L] * factor, t_byteck) - 2;  in dphy_timing_config()
283 	val[DATA] = val[CLK];  in dphy_timing_config()