Lines Matching refs:WREG32_P
227 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init()
277 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start()
280 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start()
281 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start()
291 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); in uvd_v1_0_start()
321 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start()
323 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start()
342 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
344 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
355 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
397 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_stop()
398 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_stop()
409 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_stop()
410 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_stop()