1193 	u32 gb_tiling_config = 0;  in rv770_gpu_init()  local
1335 		gb_tiling_config = PIPE_TILING(0);  in rv770_gpu_init()
1338 		gb_tiling_config = PIPE_TILING(1);  in rv770_gpu_init()
1341 		gb_tiling_config = PIPE_TILING(2);  in rv770_gpu_init()
1344 		gb_tiling_config = PIPE_TILING(3);  in rv770_gpu_init()
1358 	tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;  in rv770_gpu_init()
1361 	gb_tiling_config |= tmp << 16;  in rv770_gpu_init()
1365 		gb_tiling_config |= BANK_TILING(1);  in rv770_gpu_init()
1368 			gb_tiling_config |= BANK_TILING(1);  in rv770_gpu_init()
1370 			gb_tiling_config |= BANK_TILING(0);  in rv770_gpu_init()
1372 	rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);  in rv770_gpu_init()
1373 	gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);  in rv770_gpu_init()
1375 		gb_tiling_config |= ROW_TILING(3);  in rv770_gpu_init()
1376 		gb_tiling_config |= SAMPLE_SPLIT(3);  in rv770_gpu_init()
1378 		gb_tiling_config |=  in rv770_gpu_init()
1380 		gb_tiling_config |=  in rv770_gpu_init()
1384 	gb_tiling_config |= BANK_SWAPS(1);  in rv770_gpu_init()
1385 	rdev->config.rv770.tile_config = gb_tiling_config;  in rv770_gpu_init()
1387 	WREG32(GB_TILING_CONFIG, gb_tiling_config);  in rv770_gpu_init()
1388 	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1389 	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1390 	WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1391 	WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1393 		WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1394 		WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1395 		WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()