Lines Matching refs:rdev
33 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
43 static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev) in rv6xx_get_pi() argument
45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
50 static void rv6xx_force_pcie_gen1(struct radeon_device *rdev) in rv6xx_force_pcie_gen1() argument
63 for (i = 0; i < rdev->usec_timeout; i++) { in rv6xx_force_pcie_gen1()
74 static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev) in rv6xx_enable_pcie_gen2_support() argument
87 static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev, in rv6xx_enable_bif_dynamic_pcie_gen2() argument
100 static void rv6xx_enable_l0s(struct radeon_device *rdev) in rv6xx_enable_l0s() argument
109 static void rv6xx_enable_l1(struct radeon_device *rdev) in rv6xx_enable_l1() argument
121 static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev) in rv6xx_enable_pll_sleep_in_l1() argument
138 static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev, in rv6xx_convert_clock_to_stepping() argument
144 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in rv6xx_convert_clock_to_stepping()
159 static void rv6xx_output_stepping(struct radeon_device *rdev, in rv6xx_output_stepping() argument
162 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_output_stepping()
163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
165 u32 spll_step_count = rv6xx_scale_count_given_unit(rdev, in rv6xx_output_stepping()
170 r600_engine_clock_entry_enable(rdev, step_index, true); in rv6xx_output_stepping()
171 r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false); in rv6xx_output_stepping()
174 r600_engine_clock_entry_enable_post_divider(rdev, step_index, false); in rv6xx_output_stepping()
179 r600_engine_clock_entry_enable_post_divider(rdev, step_index, true); in rv6xx_output_stepping()
180 r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len); in rv6xx_output_stepping()
186 r600_engine_clock_entry_set_reference_divider(rdev, step_index, in rv6xx_output_stepping()
188 r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider); in rv6xx_output_stepping()
189 r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count); in rv6xx_output_stepping()
193 static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev, in rv6xx_next_vco_step() argument
209 static bool rv6xx_can_step_post_div(struct radeon_device *rdev, in rv6xx_can_step_post_div() argument
218 static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev, in rv6xx_next_post_div_step() argument
224 while (rv6xx_can_step_post_div(rdev, &next, target)) in rv6xx_next_post_div_step()
230 static bool rv6xx_reached_stepping_target(struct radeon_device *rdev, in rv6xx_reached_stepping_target() argument
239 static void rv6xx_generate_steps(struct radeon_device *rdev, in rv6xx_generate_steps() argument
248 rv6xx_convert_clock_to_stepping(rdev, low, &cur); in rv6xx_generate_steps()
249 rv6xx_convert_clock_to_stepping(rdev, high, &target); in rv6xx_generate_steps()
251 rv6xx_output_stepping(rdev, step_index++, &cur); in rv6xx_generate_steps()
261 if (rv6xx_can_step_post_div(rdev, &cur, &target)) in rv6xx_generate_steps()
262 next = rv6xx_next_post_div_step(rdev, &cur, &target); in rv6xx_generate_steps()
264 next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT); in rv6xx_generate_steps()
266 if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) { in rv6xx_generate_steps()
268 rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT); in rv6xx_generate_steps()
271 if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco)) in rv6xx_generate_steps()
272 rv6xx_output_stepping(rdev, step_index++, &tiny); in rv6xx_generate_steps()
281 rv6xx_output_stepping(rdev, step_index++, &final_vco); in rv6xx_generate_steps()
284 rv6xx_output_stepping(rdev, step_index++, &target); in rv6xx_generate_steps()
287 rv6xx_output_stepping(rdev, step_index++, &next); in rv6xx_generate_steps()
296 static void rv6xx_generate_single_step(struct radeon_device *rdev, in rv6xx_generate_single_step() argument
301 rv6xx_convert_clock_to_stepping(rdev, clock, &step); in rv6xx_generate_single_step()
302 rv6xx_output_stepping(rdev, index, &step); in rv6xx_generate_single_step()
305 static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev, in rv6xx_invalidate_intermediate_steps_range() argument
311 r600_engine_clock_entry_enable(rdev, step_index, false); in rv6xx_invalidate_intermediate_steps_range()
314 static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev, in rv6xx_set_engine_spread_spectrum_clk_s() argument
321 static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev, in rv6xx_set_engine_spread_spectrum_clk_v() argument
328 static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_engine_spread_spectrum() argument
339 static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev, in rv6xx_set_memory_spread_spectrum_clk_s() argument
345 static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev, in rv6xx_set_memory_spread_spectrum_clk_v() argument
351 static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_memory_spread_spectrum() argument
360 static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_dynamic_spread_spectrum() argument
369 static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_enable_post_divider() argument
379 static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_set_post_divider() argument
386 static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_set_feedback_divider() argument
393 static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev, in rv6xx_memory_clock_entry_set_reference_divider() argument
400 static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt) in rv6xx_vid_response_set_brt() argument
405 static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev) in rv6xx_enable_engine_feedback_and_reference_sync() argument
417 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev, in rv6xx_scale_count_given_unit() argument
425 static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev, in rv6xx_compute_count_for_delay() argument
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
430 return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit); in rv6xx_compute_count_for_delay()
433 static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_engine_speed_stepping_parameters() argument
436 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_engine_speed_stepping_parameters()
450 static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_memory_clock_stepping_parameters() argument
453 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_memory_clock_stepping_parameters()
480 static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_voltage_stepping_parameters() argument
483 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_voltage_stepping_parameters()
548 static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev, in rv6xx_program_engine_spread_spectrum() argument
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
552 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_engine_spread_spectrum()
557 rv6xx_enable_engine_spread_spectrum(rdev, level, false); in rv6xx_program_engine_spread_spectrum()
560 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { in rv6xx_program_engine_spread_spectrum()
564 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_program_engine_spread_spectrum()
575 rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v); in rv6xx_program_engine_spread_spectrum()
576 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s); in rv6xx_program_engine_spread_spectrum()
577 rv6xx_enable_engine_spread_spectrum(rdev, level, true); in rv6xx_program_engine_spread_spectrum()
583 … void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry() argument
585 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry()
587 rv6xx_program_engine_spread_spectrum(rdev, in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry()
591 rv6xx_program_engine_spread_spectrum(rdev, in rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry()
597 static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev, in rv6xx_program_mclk_stepping_entry() argument
602 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, ÷rs)) in rv6xx_program_mclk_stepping_entry()
606 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div); in rv6xx_program_mclk_stepping_entry()
607 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); in rv6xx_program_mclk_stepping_entry()
608 rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div); in rv6xx_program_mclk_stepping_entry()
611 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true); in rv6xx_program_mclk_stepping_entry()
613 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false); in rv6xx_program_mclk_stepping_entry()
618 static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_mclk_stepping_parameters_except_lowest_entry() argument
620 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mclk_stepping_parameters_except_lowest_entry()
625 rv6xx_program_mclk_stepping_entry(rdev, i, in rv6xx_program_mclk_stepping_parameters_except_lowest_entry()
630 static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev, in rv6xx_find_memory_clock_with_highest_vco() argument
636 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_find_memory_clock_with_highest_vco()
640 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, in rv6xx_find_memory_clock_with_highest_vco()
652 static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev) in rv6xx_program_mclk_spread_spectrum_parameters() argument
654 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mclk_spread_spectrum_parameters()
655 u32 ref_clk = rdev->clock.mpll.reference_freq; in rv6xx_program_mclk_spread_spectrum_parameters()
660 rv6xx_enable_memory_spread_spectrum(rdev, false); in rv6xx_program_mclk_spread_spectrum_parameters()
663 rv6xx_find_memory_clock_with_highest_vco(rdev, in rv6xx_program_mclk_spread_spectrum_parameters()
669 rv6xx_find_memory_clock_with_highest_vco(rdev, in rv6xx_program_mclk_spread_spectrum_parameters()
675 rv6xx_find_memory_clock_with_highest_vco(rdev, in rv6xx_program_mclk_spread_spectrum_parameters()
682 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_program_mclk_spread_spectrum_parameters()
693 rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v); in rv6xx_program_mclk_spread_spectrum_parameters()
694 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s); in rv6xx_program_mclk_spread_spectrum_parameters()
695 rv6xx_enable_memory_spread_spectrum(rdev, true); in rv6xx_program_mclk_spread_spectrum_parameters()
701 static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev, in rv6xx_program_voltage_stepping_entry() argument
707 ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage, in rv6xx_program_voltage_stepping_entry()
713 r600_voltage_control_program_voltages(rdev, entry, set_pins); in rv6xx_program_voltage_stepping_entry()
718 …atic void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_voltage_stepping_parameters_except_lowest_entry() argument
720 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_voltage_stepping_parameters_except_lowest_entry()
724 rv6xx_program_voltage_stepping_entry(rdev, i, in rv6xx_program_voltage_stepping_parameters_except_lowest_entry()
729 …tic void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_backbias_stepping_parameters_except_lowest_entry() argument
731 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
744 static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry() argument
746 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry()
748 rv6xx_program_engine_spread_spectrum(rdev, in rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry()
753 static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_mclk_stepping_parameters_lowest_entry() argument
755 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mclk_stepping_parameters_lowest_entry()
758 rv6xx_program_mclk_stepping_entry(rdev, 0, in rv6xx_program_mclk_stepping_parameters_lowest_entry()
762 static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_voltage_stepping_parameters_lowest_entry() argument
764 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_voltage_stepping_parameters_lowest_entry()
766 rv6xx_program_voltage_stepping_entry(rdev, 0, in rv6xx_program_voltage_stepping_parameters_lowest_entry()
771 static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_backbias_stepping_parameters_lowest_entry() argument
773 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_backbias_stepping_parameters_lowest_entry()
781 static u32 calculate_memory_refresh_rate(struct radeon_device *rdev, in calculate_memory_refresh_rate() argument
794 static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev) in rv6xx_program_memory_timing_parameters() argument
796 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_memory_timing_parameters()
808 radeon_atom_set_engine_dram_timings(rdev, high_clock, 0); in rv6xx_program_memory_timing_parameters()
817 (POWERMODE0(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
819 POWERMODE1(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
821 POWERMODE2(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
823 POWERMODE3(calculate_memory_refresh_rate(rdev, in rv6xx_program_memory_timing_parameters()
828 static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev) in rv6xx_program_mpll_timing_parameters() argument
830 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_mpll_timing_parameters()
832 r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT * in rv6xx_program_mpll_timing_parameters()
834 r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT); in rv6xx_program_mpll_timing_parameters()
837 static void rv6xx_program_bsp(struct radeon_device *rdev) in rv6xx_program_bsp() argument
839 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_bsp()
840 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
847 r600_set_bsp(rdev, pi->bsu, pi->bsp); in rv6xx_program_bsp()
850 static void rv6xx_program_at(struct radeon_device *rdev) in rv6xx_program_at() argument
852 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_at()
854 r600_set_at(rdev, in rv6xx_program_at()
861 static void rv6xx_program_git(struct radeon_device *rdev) in rv6xx_program_git() argument
863 r600_set_git(rdev, R600_GICST_DFLT); in rv6xx_program_git()
866 static void rv6xx_program_tp(struct radeon_device *rdev) in rv6xx_program_tp() argument
871 r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]); in rv6xx_program_tp()
873 r600_select_td(rdev, R600_TD_DFLT); in rv6xx_program_tp()
876 static void rv6xx_program_vc(struct radeon_device *rdev) in rv6xx_program_vc() argument
878 r600_set_vrc(rdev, R600_VRC_DFLT); in rv6xx_program_vc()
881 static void rv6xx_clear_vc(struct radeon_device *rdev) in rv6xx_clear_vc() argument
883 r600_set_vrc(rdev, 0); in rv6xx_clear_vc()
886 static void rv6xx_program_tpp(struct radeon_device *rdev) in rv6xx_program_tpp() argument
888 r600_set_tpu(rdev, R600_TPU_DFLT); in rv6xx_program_tpp()
889 r600_set_tpc(rdev, R600_TPC_DFLT); in rv6xx_program_tpp()
892 static void rv6xx_program_sstp(struct radeon_device *rdev) in rv6xx_program_sstp() argument
894 r600_set_sstu(rdev, R600_SSTU_DFLT); in rv6xx_program_sstp()
895 r600_set_sst(rdev, R600_SST_DFLT); in rv6xx_program_sstp()
898 static void rv6xx_program_fcp(struct radeon_device *rdev) in rv6xx_program_fcp() argument
900 r600_set_fctu(rdev, R600_FCTU_DFLT); in rv6xx_program_fcp()
901 r600_set_fct(rdev, R600_FCT_DFLT); in rv6xx_program_fcp()
904 static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev) in rv6xx_program_vddc3d_parameters() argument
906 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT); in rv6xx_program_vddc3d_parameters()
907 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT); in rv6xx_program_vddc3d_parameters()
908 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT); in rv6xx_program_vddc3d_parameters()
909 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT); in rv6xx_program_vddc3d_parameters()
910 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT); in rv6xx_program_vddc3d_parameters()
913 static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev) in rv6xx_program_voltage_timing_parameters() argument
917 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT); in rv6xx_program_voltage_timing_parameters()
919 r600_vid_rt_set_vrt(rdev, in rv6xx_program_voltage_timing_parameters()
920 rv6xx_compute_count_for_delay(rdev, in rv6xx_program_voltage_timing_parameters()
921 rdev->pm.dpm.voltage_response_time, in rv6xx_program_voltage_timing_parameters()
924 rt = rv6xx_compute_count_for_delay(rdev, in rv6xx_program_voltage_timing_parameters()
925 rdev->pm.dpm.backbias_response_time, in rv6xx_program_voltage_timing_parameters()
928 rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5); in rv6xx_program_voltage_timing_parameters()
931 static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev) in rv6xx_program_engine_speed_parameters() argument
933 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT); in rv6xx_program_engine_speed_parameters()
934 rv6xx_enable_engine_feedback_and_reference_sync(rdev); in rv6xx_program_engine_speed_parameters()
937 static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev) in rv6xx_get_master_voltage_mask() argument
939 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_get_master_voltage_mask()
947 ret = radeon_atom_get_voltage_gpio_settings(rdev, in rv6xx_get_master_voltage_mask()
959 static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev) in rv6xx_program_voltage_gpio_pins() argument
961 r600_voltage_control_enable_pins(rdev, in rv6xx_program_voltage_gpio_pins()
962 rv6xx_get_master_voltage_mask(rdev)); in rv6xx_program_voltage_gpio_pins()
965 static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev, in rv6xx_enable_static_voltage_control() argument
972 radeon_atom_set_voltage(rdev, in rv6xx_enable_static_voltage_control()
976 r600_voltage_control_deactivate_static_control(rdev, in rv6xx_enable_static_voltage_control()
977 rv6xx_get_master_voltage_mask(rdev)); in rv6xx_enable_static_voltage_control()
980 static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable) in rv6xx_enable_display_gap() argument
996 static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev) in rv6xx_program_power_level_enter_state() argument
998 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM); in rv6xx_program_power_level_enter_state()
1018 static void rv6xx_calculate_ap(struct radeon_device *rdev, in rv6xx_calculate_ap() argument
1021 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_calculate_ap()
1045 static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev, in rv6xx_calculate_stepping_parameters() argument
1050 rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1051 rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1052 rv6xx_calculate_voltage_stepping_parameters(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1053 rv6xx_calculate_ap(rdev, new_state); in rv6xx_calculate_stepping_parameters()
1056 static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev) in rv6xx_program_stepping_parameters_except_lowest_entry() argument
1058 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1060 rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1062 rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1063 rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1064 rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1065 rv6xx_program_mclk_spread_spectrum_parameters(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1066 rv6xx_program_memory_timing_parameters(rdev); in rv6xx_program_stepping_parameters_except_lowest_entry()
1069 static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev) in rv6xx_program_stepping_parameters_lowest_entry() argument
1071 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1073 rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1075 rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1076 rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1077 rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev); in rv6xx_program_stepping_parameters_lowest_entry()
1080 static void rv6xx_program_power_level_low(struct radeon_device *rdev) in rv6xx_program_power_level_low() argument
1082 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_low()
1084 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1086 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1088 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1090 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1092 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low()
1096 static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev) in rv6xx_program_power_level_low_to_lowest_state() argument
1098 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_low_to_lowest_state()
1100 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0); in rv6xx_program_power_level_low_to_lowest_state()
1101 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); in rv6xx_program_power_level_low_to_lowest_state()
1102 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0); in rv6xx_program_power_level_low_to_lowest_state()
1104 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low_to_lowest_state()
1107 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW, in rv6xx_program_power_level_low_to_lowest_state()
1112 static void rv6xx_program_power_level_medium(struct radeon_device *rdev) in rv6xx_program_power_level_medium() argument
1114 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_medium()
1116 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1118 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1120 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1122 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1124 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium()
1128 static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev) in rv6xx_program_power_level_medium_for_transition() argument
1130 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_medium_for_transition()
1132 rv6xx_program_mclk_stepping_entry(rdev, in rv6xx_program_power_level_medium_for_transition()
1136 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1); in rv6xx_program_power_level_medium_for_transition()
1138 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1140 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1143 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1146 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_program_power_level_medium_for_transition()
1148 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM, in rv6xx_program_power_level_medium_for_transition()
1152 static void rv6xx_program_power_level_high(struct radeon_device *rdev) in rv6xx_program_power_level_high() argument
1154 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_program_power_level_high()
1156 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1158 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1160 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1163 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1166 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH, in rv6xx_program_power_level_high()
1170 static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable) in rv6xx_enable_backbias() argument
1180 static void rv6xx_program_display_gap(struct radeon_device *rdev) in rv6xx_program_display_gap() argument
1185 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv6xx_program_display_gap()
1188 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv6xx_program_display_gap()
1198 static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev, in rv6xx_set_sw_voltage_to_safe() argument
1209 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, in rv6xx_set_sw_voltage_to_safe()
1216 static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev, in rv6xx_set_sw_voltage_to_low() argument
1221 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, in rv6xx_set_sw_voltage_to_low()
1228 static void rv6xx_set_safe_backbias(struct radeon_device *rdev, in rv6xx_set_safe_backbias() argument
1242 static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev, in rv6xx_set_safe_pcie_gen2() argument
1251 rv6xx_force_pcie_gen1(rdev); in rv6xx_set_safe_pcie_gen2()
1254 static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev, in rv6xx_enable_dynamic_voltage_control() argument
1263 static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev, in rv6xx_enable_dynamic_backbias_control() argument
1272 static int rv6xx_step_sw_voltage(struct radeon_device *rdev, in rv6xx_step_sw_voltage() argument
1281 if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in rv6xx_step_sw_voltage()
1283 (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in rv6xx_step_sw_voltage()
1285 (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, in rv6xx_step_sw_voltage()
1296 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW, in rv6xx_step_sw_voltage()
1298 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); in rv6xx_step_sw_voltage()
1304 static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev, in rv6xx_step_voltage_if_increasing() argument
1312 return rv6xx_step_sw_voltage(rdev, in rv6xx_step_voltage_if_increasing()
1319 static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev, in rv6xx_step_voltage_if_decreasing() argument
1327 return rv6xx_step_sw_voltage(rdev, in rv6xx_step_voltage_if_decreasing()
1334 static void rv6xx_enable_high(struct radeon_device *rdev) in rv6xx_enable_high() argument
1336 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_high()
1340 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true); in rv6xx_enable_high()
1343 static void rv6xx_enable_medium(struct radeon_device *rdev) in rv6xx_enable_medium() argument
1345 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_medium()
1348 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_enable_medium()
1351 static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) in rv6xx_set_dpm_event_sources() argument
1353 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_set_dpm_event_sources()
1388 static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev, in rv6xx_enable_auto_throttle_source() argument
1392 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_auto_throttle_source()
1397 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in rv6xx_enable_auto_throttle_source()
1402 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in rv6xx_enable_auto_throttle_source()
1408 static void rv6xx_enable_thermal_protection(struct radeon_device *rdev, in rv6xx_enable_thermal_protection() argument
1411 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_enable_thermal_protection()
1414 r600_enable_thermal_protection(rdev, enable); in rv6xx_enable_thermal_protection()
1417 static void rv6xx_generate_transition_stepping(struct radeon_device *rdev, in rv6xx_generate_transition_stepping() argument
1423 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_generate_transition_stepping()
1425 rv6xx_generate_steps(rdev, in rv6xx_generate_transition_stepping()
1431 static void rv6xx_generate_low_step(struct radeon_device *rdev, in rv6xx_generate_low_step() argument
1435 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_generate_low_step()
1438 rv6xx_generate_single_step(rdev, in rv6xx_generate_low_step()
1443 static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev) in rv6xx_invalidate_intermediate_steps() argument
1445 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_invalidate_intermediate_steps()
1447 rv6xx_invalidate_intermediate_steps_range(rdev, 0, in rv6xx_invalidate_intermediate_steps()
1451 static void rv6xx_generate_stepping_table(struct radeon_device *rdev, in rv6xx_generate_stepping_table() argument
1455 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_generate_stepping_table()
1459 rv6xx_generate_steps(rdev, in rv6xx_generate_stepping_table()
1464 rv6xx_generate_steps(rdev, in rv6xx_generate_stepping_table()
1471 static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev, in rv6xx_enable_spread_spectrum() argument
1475 rv6xx_enable_dynamic_spread_spectrum(rdev, true); in rv6xx_enable_spread_spectrum()
1477 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false); in rv6xx_enable_spread_spectrum()
1478 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_enable_spread_spectrum()
1479 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_enable_spread_spectrum()
1480 rv6xx_enable_dynamic_spread_spectrum(rdev, false); in rv6xx_enable_spread_spectrum()
1481 rv6xx_enable_memory_spread_spectrum(rdev, false); in rv6xx_enable_spread_spectrum()
1485 static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev) in rv6xx_reset_lvtm_data_sync() argument
1487 if (ASIC_IS_DCE3(rdev)) in rv6xx_reset_lvtm_data_sync()
1493 static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev, in rv6xx_enable_dynamic_pcie_gen2() argument
1500 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true); in rv6xx_enable_dynamic_pcie_gen2()
1501 rv6xx_enable_pcie_gen2_support(rdev); in rv6xx_enable_dynamic_pcie_gen2()
1502 r600_enable_dynamic_pcie_gen2(rdev, true); in rv6xx_enable_dynamic_pcie_gen2()
1505 rv6xx_force_pcie_gen1(rdev); in rv6xx_enable_dynamic_pcie_gen2()
1506 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false); in rv6xx_enable_dynamic_pcie_gen2()
1507 r600_enable_dynamic_pcie_gen2(rdev, false); in rv6xx_enable_dynamic_pcie_gen2()
1511 static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, in rv6xx_set_uvd_clock_before_set_eng_clock() argument
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1528 static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, in rv6xx_set_uvd_clock_after_set_eng_clock() argument
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1545 int rv6xx_dpm_enable(struct radeon_device *rdev) in rv6xx_dpm_enable() argument
1547 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_enable()
1548 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_enable()
1550 if (r600_dynamicpm_enabled(rdev)) in rv6xx_dpm_enable()
1553 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_enable()
1554 rv6xx_enable_backbias(rdev, true); in rv6xx_dpm_enable()
1557 rv6xx_enable_spread_spectrum(rdev, true); in rv6xx_dpm_enable()
1559 rv6xx_program_mpll_timing_parameters(rdev); in rv6xx_dpm_enable()
1560 rv6xx_program_bsp(rdev); in rv6xx_dpm_enable()
1561 rv6xx_program_git(rdev); in rv6xx_dpm_enable()
1562 rv6xx_program_tp(rdev); in rv6xx_dpm_enable()
1563 rv6xx_program_tpp(rdev); in rv6xx_dpm_enable()
1564 rv6xx_program_sstp(rdev); in rv6xx_dpm_enable()
1565 rv6xx_program_fcp(rdev); in rv6xx_dpm_enable()
1566 rv6xx_program_vddc3d_parameters(rdev); in rv6xx_dpm_enable()
1567 rv6xx_program_voltage_timing_parameters(rdev); in rv6xx_dpm_enable()
1568 rv6xx_program_engine_speed_parameters(rdev); in rv6xx_dpm_enable()
1570 rv6xx_enable_display_gap(rdev, true); in rv6xx_dpm_enable()
1572 rv6xx_enable_display_gap(rdev, false); in rv6xx_dpm_enable()
1574 rv6xx_program_power_level_enter_state(rdev); in rv6xx_dpm_enable()
1576 rv6xx_calculate_stepping_parameters(rdev, boot_ps); in rv6xx_dpm_enable()
1579 rv6xx_program_voltage_gpio_pins(rdev); in rv6xx_dpm_enable()
1581 rv6xx_generate_stepping_table(rdev, boot_ps); in rv6xx_dpm_enable()
1583 rv6xx_program_stepping_parameters_except_lowest_entry(rdev); in rv6xx_dpm_enable()
1584 rv6xx_program_stepping_parameters_lowest_entry(rdev); in rv6xx_dpm_enable()
1586 rv6xx_program_power_level_low(rdev); in rv6xx_dpm_enable()
1587 rv6xx_program_power_level_medium(rdev); in rv6xx_dpm_enable()
1588 rv6xx_program_power_level_high(rdev); in rv6xx_dpm_enable()
1589 rv6xx_program_vc(rdev); in rv6xx_dpm_enable()
1590 rv6xx_program_at(rdev); in rv6xx_dpm_enable()
1592 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_enable()
1593 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_dpm_enable()
1594 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true); in rv6xx_dpm_enable()
1596 rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); in rv6xx_dpm_enable()
1598 r600_start_dpm(rdev); in rv6xx_dpm_enable()
1601 rv6xx_enable_static_voltage_control(rdev, boot_ps, false); in rv6xx_dpm_enable()
1604 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true); in rv6xx_dpm_enable()
1607 r600_gfx_clockgating_enable(rdev, true); in rv6xx_dpm_enable()
1612 void rv6xx_dpm_disable(struct radeon_device *rdev) in rv6xx_dpm_disable() argument
1614 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_disable()
1615 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_disable()
1617 if (!r600_dynamicpm_enabled(rdev)) in rv6xx_dpm_disable()
1620 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_disable()
1621 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_dpm_disable()
1622 rv6xx_enable_display_gap(rdev, false); in rv6xx_dpm_disable()
1623 rv6xx_clear_vc(rdev); in rv6xx_dpm_disable()
1624 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); in rv6xx_dpm_disable()
1627 r600_enable_thermal_protection(rdev, false); in rv6xx_dpm_disable()
1629 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_disable()
1630 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_dpm_disable()
1631 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_disable()
1633 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_disable()
1634 rv6xx_enable_backbias(rdev, false); in rv6xx_dpm_disable()
1636 rv6xx_enable_spread_spectrum(rdev, false); in rv6xx_dpm_disable()
1639 rv6xx_enable_static_voltage_control(rdev, boot_ps, true); in rv6xx_dpm_disable()
1642 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false); in rv6xx_dpm_disable()
1644 if (rdev->irq.installed && in rv6xx_dpm_disable()
1645 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in rv6xx_dpm_disable()
1646 rdev->irq.dpm_thermal = false; in rv6xx_dpm_disable()
1647 radeon_irq_set(rdev); in rv6xx_dpm_disable()
1651 r600_gfx_clockgating_enable(rdev, false); in rv6xx_dpm_disable()
1653 r600_stop_dpm(rdev); in rv6xx_dpm_disable()
1656 int rv6xx_dpm_set_power_state(struct radeon_device *rdev) in rv6xx_dpm_set_power_state() argument
1658 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_set_power_state()
1659 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in rv6xx_dpm_set_power_state()
1660 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; in rv6xx_dpm_set_power_state()
1665 rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1667 rv6xx_clear_vc(rdev); in rv6xx_dpm_set_power_state()
1668 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_set_power_state()
1669 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); in rv6xx_dpm_set_power_state()
1672 r600_enable_thermal_protection(rdev, false); in rv6xx_dpm_set_power_state()
1674 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_set_power_state()
1675 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_dpm_set_power_state()
1676 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_set_power_state()
1678 rv6xx_generate_transition_stepping(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1679 rv6xx_program_power_level_medium_for_transition(rdev); in rv6xx_dpm_set_power_state()
1682 rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1683 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv6xx_dpm_set_power_state()
1684 rv6xx_set_sw_voltage_to_low(rdev, old_ps); in rv6xx_dpm_set_power_state()
1687 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_set_power_state()
1688 rv6xx_set_safe_backbias(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1691 rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1694 rv6xx_enable_dynamic_voltage_control(rdev, false); in rv6xx_dpm_set_power_state()
1696 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_set_power_state()
1697 rv6xx_enable_dynamic_backbias_control(rdev, false); in rv6xx_dpm_set_power_state()
1700 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv6xx_dpm_set_power_state()
1701 rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1702 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); in rv6xx_dpm_set_power_state()
1705 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true); in rv6xx_dpm_set_power_state()
1706 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false); in rv6xx_dpm_set_power_state()
1707 r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_set_power_state()
1709 rv6xx_generate_low_step(rdev, new_ps); in rv6xx_dpm_set_power_state()
1710 rv6xx_invalidate_intermediate_steps(rdev); in rv6xx_dpm_set_power_state()
1711 rv6xx_calculate_stepping_parameters(rdev, new_ps); in rv6xx_dpm_set_power_state()
1712 rv6xx_program_stepping_parameters_lowest_entry(rdev); in rv6xx_dpm_set_power_state()
1713 rv6xx_program_power_level_low_to_lowest_state(rdev); in rv6xx_dpm_set_power_state()
1715 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_set_power_state()
1716 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_set_power_state()
1717 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_set_power_state()
1720 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) { in rv6xx_dpm_set_power_state()
1721 ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1725 rv6xx_enable_dynamic_voltage_control(rdev, true); in rv6xx_dpm_set_power_state()
1728 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_set_power_state()
1729 rv6xx_enable_dynamic_backbias_control(rdev, true); in rv6xx_dpm_set_power_state()
1732 rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true); in rv6xx_dpm_set_power_state()
1734 rv6xx_reset_lvtm_data_sync(rdev); in rv6xx_dpm_set_power_state()
1736 rv6xx_generate_stepping_table(rdev, new_ps); in rv6xx_dpm_set_power_state()
1737 rv6xx_program_stepping_parameters_except_lowest_entry(rdev); in rv6xx_dpm_set_power_state()
1738 rv6xx_program_power_level_low(rdev); in rv6xx_dpm_set_power_state()
1739 rv6xx_program_power_level_medium(rdev); in rv6xx_dpm_set_power_state()
1740 rv6xx_program_power_level_high(rdev); in rv6xx_dpm_set_power_state()
1741 rv6xx_enable_medium(rdev); in rv6xx_dpm_set_power_state()
1742 rv6xx_enable_high(rdev); in rv6xx_dpm_set_power_state()
1745 rv6xx_enable_thermal_protection(rdev, true); in rv6xx_dpm_set_power_state()
1746 rv6xx_program_vc(rdev); in rv6xx_dpm_set_power_state()
1747 rv6xx_program_at(rdev); in rv6xx_dpm_set_power_state()
1749 rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); in rv6xx_dpm_set_power_state()
1754 void rv6xx_setup_asic(struct radeon_device *rdev) in rv6xx_setup_asic() argument
1756 r600_enable_acpi_pm(rdev); in rv6xx_setup_asic()
1759 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s) in rv6xx_setup_asic()
1760 rv6xx_enable_l0s(rdev); in rv6xx_setup_asic()
1761 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1) in rv6xx_setup_asic()
1762 rv6xx_enable_l1(rdev); in rv6xx_setup_asic()
1763 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1) in rv6xx_setup_asic()
1764 rv6xx_enable_pll_sleep_in_l1(rdev); in rv6xx_setup_asic()
1768 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev) in rv6xx_dpm_display_configuration_changed() argument
1770 rv6xx_program_display_gap(rdev); in rv6xx_dpm_display_configuration_changed()
1794 static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev, in rv6xx_parse_pplib_non_clock_info() argument
1811 rdev->pm.dpm.boot_ps = rps; in rv6xx_parse_pplib_non_clock_info()
1813 rdev->pm.dpm.uvd_ps = rps; in rv6xx_parse_pplib_non_clock_info()
1816 static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev, in rv6xx_parse_pplib_clock_info() argument
1850 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0) in rv6xx_parse_pplib_clock_info()
1856 if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) { in rv6xx_parse_pplib_clock_info()
1865 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); in rv6xx_parse_pplib_clock_info()
1866 pl->mclk = rdev->clock.default_mclk; in rv6xx_parse_pplib_clock_info()
1867 pl->sclk = rdev->clock.default_sclk; in rv6xx_parse_pplib_clock_info()
1872 static int rv6xx_parse_power_table(struct radeon_device *rdev) in rv6xx_parse_power_table() argument
1874 struct radeon_mode_info *mode_info = &rdev->mode_info; in rv6xx_parse_power_table()
1890 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates, in rv6xx_parse_power_table()
1893 if (!rdev->pm.dpm.ps) in rv6xx_parse_power_table()
1910 kfree(rdev->pm.dpm.ps); in rv6xx_parse_power_table()
1913 rdev->pm.dpm.ps[i].ps_priv = ps; in rv6xx_parse_power_table()
1914 rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in rv6xx_parse_power_table()
1922 rv6xx_parse_pplib_clock_info(rdev, in rv6xx_parse_power_table()
1923 &rdev->pm.dpm.ps[i], j, in rv6xx_parse_power_table()
1928 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates; in rv6xx_parse_power_table()
1932 int rv6xx_dpm_init(struct radeon_device *rdev) in rv6xx_dpm_init() argument
1942 rdev->pm.dpm.priv = pi; in rv6xx_dpm_init()
1944 ret = r600_get_platform_caps(rdev); in rv6xx_dpm_init()
1948 ret = rv6xx_parse_power_table(rdev); in rv6xx_dpm_init()
1952 if (rdev->pm.dpm.voltage_response_time == 0) in rv6xx_dpm_init()
1953 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in rv6xx_dpm_init()
1954 if (rdev->pm.dpm.backbias_response_time == 0) in rv6xx_dpm_init()
1955 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in rv6xx_dpm_init()
1957 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in rv6xx_dpm_init()
1964 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, in rv6xx_dpm_init()
1971 if (rdev->family >= CHIP_RV670) in rv6xx_dpm_init()
1977 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0); in rv6xx_dpm_init()
1981 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_dpm_init()
1983 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss, in rv6xx_dpm_init()
1997 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)) in rv6xx_dpm_init()
2007 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, in rv6xx_dpm_print_power_state() argument
2025 r600_dpm_print_ps_status(rdev, rps); in rv6xx_dpm_print_power_state()
2028 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, in rv6xx_dpm_debugfs_print_current_performance_level() argument
2031 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv6xx_dpm_debugfs_print_current_performance_level()
2054 u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev) in rv6xx_dpm_get_current_sclk() argument
2056 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv6xx_dpm_get_current_sclk()
2077 u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev) in rv6xx_dpm_get_current_mclk() argument
2079 struct radeon_ps *rps = rdev->pm.dpm.current_ps; in rv6xx_dpm_get_current_mclk()
2099 void rv6xx_dpm_fini(struct radeon_device *rdev) in rv6xx_dpm_fini() argument
2103 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in rv6xx_dpm_fini()
2104 kfree(rdev->pm.dpm.ps[i].ps_priv); in rv6xx_dpm_fini()
2106 kfree(rdev->pm.dpm.ps); in rv6xx_dpm_fini()
2107 kfree(rdev->pm.dpm.priv); in rv6xx_dpm_fini()
2110 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low) in rv6xx_dpm_get_sclk() argument
2112 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); in rv6xx_dpm_get_sclk()
2120 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low) in rv6xx_dpm_get_mclk() argument
2122 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps); in rv6xx_dpm_get_mclk()
2130 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, in rv6xx_dpm_force_performance_level() argument
2133 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev); in rv6xx_dpm_force_performance_level()
2143 rv6xx_clear_vc(rdev); in rv6xx_dpm_force_performance_level()
2144 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true); in rv6xx_dpm_force_performance_level()
2145 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF); in rv6xx_dpm_force_performance_level()
2146 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW); in rv6xx_dpm_force_performance_level()
2147 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false); in rv6xx_dpm_force_performance_level()
2148 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false); in rv6xx_dpm_force_performance_level()
2149 rv6xx_enable_medium(rdev); in rv6xx_dpm_force_performance_level()
2150 rv6xx_enable_high(rdev); in rv6xx_dpm_force_performance_level()
2152 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false); in rv6xx_dpm_force_performance_level()
2153 rv6xx_program_vc(rdev); in rv6xx_dpm_force_performance_level()
2154 rv6xx_program_at(rdev); in rv6xx_dpm_force_performance_level()
2156 rdev->pm.dpm.forced_level = level; in rv6xx_dpm_force_performance_level()