54 static void rs600_gpu_init(struct radeon_device *rdev);
55 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
63 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)  in avivo_is_in_vblank()  argument
71 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)  in avivo_is_counter_moving()  argument
92 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)  in avivo_wait_for_vblank()  argument
96 	if (crtc >= rdev->num_crtc)  in avivo_wait_for_vblank()
105 	while (avivo_is_in_vblank(rdev, crtc)) {  in avivo_wait_for_vblank()
107 			if (!avivo_is_counter_moving(rdev, crtc))  in avivo_wait_for_vblank()
112 	while (!avivo_is_in_vblank(rdev, crtc)) {  in avivo_wait_for_vblank()
114 			if (!avivo_is_counter_moving(rdev, crtc))  in avivo_wait_for_vblank()
120 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)  in rs600_page_flip()  argument
122 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in rs600_page_flip()
144 	for (i = 0; i < rdev->usec_timeout; i++) {  in rs600_page_flip()
156 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)  in rs600_page_flip_pending()  argument
158 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in rs600_page_flip_pending()
168 	struct radeon_device *rdev = dev->dev_private;  in avivo_program_fmt()  local
229 void rs600_pm_misc(struct radeon_device *rdev)  in rs600_pm_misc()  argument
231 	int requested_index = rdev->pm.requested_power_state_index;  in rs600_pm_misc()
232 	struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];  in rs600_pm_misc()
258 		radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);  in rs600_pm_misc()
312 	if ((rdev->flags & RADEON_IS_PCIE) &&  in rs600_pm_misc()
313 	    !(rdev->flags & RADEON_IS_IGP) &&  in rs600_pm_misc()
314 	    rdev->asic->pm.set_pcie_lanes &&  in rs600_pm_misc()
316 	     rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {  in rs600_pm_misc()
317 		radeon_set_pcie_lanes(rdev,  in rs600_pm_misc()
323 void rs600_pm_prepare(struct radeon_device *rdev)  in rs600_pm_prepare()  argument
325 	struct drm_device *ddev = rdev->ddev;  in rs600_pm_prepare()
341 void rs600_pm_finish(struct radeon_device *rdev)  in rs600_pm_finish()  argument
343 	struct drm_device *ddev = rdev->ddev;  in rs600_pm_finish()
360 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)  in rs600_hpd_sense()  argument
382 void rs600_hpd_set_polarity(struct radeon_device *rdev,  in rs600_hpd_set_polarity()  argument
386 	bool connected = rs600_hpd_sense(rdev, hpd);  in rs600_hpd_set_polarity()
410 void rs600_hpd_init(struct radeon_device *rdev)  in rs600_hpd_init()  argument
412 	struct drm_device *dev = rdev->ddev;  in rs600_hpd_init()
432 		radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);  in rs600_hpd_init()
434 	radeon_irq_kms_enable_hpd(rdev, enable);  in rs600_hpd_init()
437 void rs600_hpd_fini(struct radeon_device *rdev)  in rs600_hpd_fini()  argument
439 	struct drm_device *dev = rdev->ddev;  in rs600_hpd_fini()
460 	radeon_irq_kms_disable_hpd(rdev, disable);  in rs600_hpd_fini()
463 int rs600_asic_reset(struct radeon_device *rdev, bool hard)  in rs600_asic_reset()  argument
474 	rv515_mc_stop(rdev, &save);  in rs600_asic_reset()
476 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in rs600_asic_reset()
484 	pci_save_state(rdev->pdev);  in rs600_asic_reset()
486 	pci_clear_master(rdev->pdev);  in rs600_asic_reset()
496 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in rs600_asic_reset()
504 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in rs600_asic_reset()
512 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in rs600_asic_reset()
514 	pci_restore_state(rdev->pdev);  in rs600_asic_reset()
517 		dev_err(rdev->dev, "failed to reset GPU\n");  in rs600_asic_reset()
520 		dev_info(rdev->dev, "GPU reset succeed\n");  in rs600_asic_reset()
521 	rv515_mc_resume(rdev, &save);  in rs600_asic_reset()
528 void rs600_gart_tlb_flush(struct radeon_device *rdev)  in rs600_gart_tlb_flush()  argument
546 static int rs600_gart_init(struct radeon_device *rdev)  in rs600_gart_init()  argument
550 	if (rdev->gart.robj) {  in rs600_gart_init()
555 	r = radeon_gart_init(rdev);  in rs600_gart_init()
559 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;  in rs600_gart_init()
560 	return radeon_gart_table_vram_alloc(rdev);  in rs600_gart_init()
563 static int rs600_gart_enable(struct radeon_device *rdev)  in rs600_gart_enable()  argument
568 	if (rdev->gart.robj == NULL) {  in rs600_gart_enable()
569 		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");  in rs600_gart_enable()
572 	r = radeon_gart_table_vram_pin(rdev);  in rs600_gart_enable()
605 		  rdev->gart.table_addr);  in rs600_gart_enable()
606 	WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);  in rs600_gart_enable()
607 	WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);  in rs600_gart_enable()
611 	WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);  in rs600_gart_enable()
612 	WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);  in rs600_gart_enable()
619 	rs600_gart_tlb_flush(rdev);  in rs600_gart_enable()
621 		 (unsigned)(rdev->mc.gtt_size >> 20),  in rs600_gart_enable()
622 		 (unsigned long long)rdev->gart.table_addr);  in rs600_gart_enable()
623 	rdev->gart.ready = true;  in rs600_gart_enable()
627 static void rs600_gart_disable(struct radeon_device *rdev)  in rs600_gart_disable()  argument
635 	radeon_gart_table_vram_unpin(rdev);  in rs600_gart_disable()
638 static void rs600_gart_fini(struct radeon_device *rdev)  in rs600_gart_fini()  argument
640 	radeon_gart_fini(rdev);  in rs600_gart_fini()
641 	rs600_gart_disable(rdev);  in rs600_gart_fini()
642 	radeon_gart_table_vram_free(rdev);  in rs600_gart_fini()
660 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,  in rs600_gart_set_page()  argument
663 	void __iomem *ptr = (void *)rdev->gart.ptr;  in rs600_gart_set_page()
667 int rs600_irq_set(struct radeon_device *rdev)  in rs600_irq_set()  argument
676 	if (ASIC_IS_DCE2(rdev))  in rs600_irq_set()
682 	if (!rdev->irq.installed) {  in rs600_irq_set()
687 	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {  in rs600_irq_set()
690 	if (rdev->irq.crtc_vblank_int[0] ||  in rs600_irq_set()
691 	    atomic_read(&rdev->irq.pflip[0])) {  in rs600_irq_set()
694 	if (rdev->irq.crtc_vblank_int[1] ||  in rs600_irq_set()
695 	    atomic_read(&rdev->irq.pflip[1])) {  in rs600_irq_set()
698 	if (rdev->irq.hpd[0]) {  in rs600_irq_set()
701 	if (rdev->irq.hpd[1]) {  in rs600_irq_set()
704 	if (rdev->irq.afmt[0]) {  in rs600_irq_set()
711 	if (ASIC_IS_DCE2(rdev))  in rs600_irq_set()
720 static inline u32 rs600_irq_ack(struct radeon_device *rdev)  in rs600_irq_ack()  argument
727 		rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);  in rs600_irq_ack()
728 		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_ack()
732 		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_ack()
736 		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_ack()
741 		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_ack()
747 		rdev->irq.stat_regs.r500.disp_int = 0;  in rs600_irq_ack()
750 	if (ASIC_IS_DCE2(rdev)) {  in rs600_irq_ack()
751 		rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &  in rs600_irq_ack()
753 		if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {  in rs600_irq_ack()
759 		rdev->irq.stat_regs.r500.hdmi0_status = 0;  in rs600_irq_ack()
767 void rs600_irq_disable(struct radeon_device *rdev)  in rs600_irq_disable()  argument
776 	rs600_irq_ack(rdev);  in rs600_irq_disable()
779 int rs600_irq_process(struct radeon_device *rdev)  in rs600_irq_process()  argument
785 	status = rs600_irq_ack(rdev);  in rs600_irq_process()
787 	    !rdev->irq.stat_regs.r500.disp_int &&  in rs600_irq_process()
788 	    !rdev->irq.stat_regs.r500.hdmi0_status) {  in rs600_irq_process()
792 	       rdev->irq.stat_regs.r500.disp_int ||  in rs600_irq_process()
793 	       rdev->irq.stat_regs.r500.hdmi0_status) {  in rs600_irq_process()
796 			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);  in rs600_irq_process()
799 		if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_process()
800 			if (rdev->irq.crtc_vblank_int[0]) {  in rs600_irq_process()
801 				drm_handle_vblank(rdev->ddev, 0);  in rs600_irq_process()
802 				rdev->pm.vblank_sync = true;  in rs600_irq_process()
803 				wake_up(&rdev->irq.vblank_queue);  in rs600_irq_process()
805 			if (atomic_read(&rdev->irq.pflip[0]))  in rs600_irq_process()
806 				radeon_crtc_handle_vblank(rdev, 0);  in rs600_irq_process()
808 		if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_process()
809 			if (rdev->irq.crtc_vblank_int[1]) {  in rs600_irq_process()
810 				drm_handle_vblank(rdev->ddev, 1);  in rs600_irq_process()
811 				rdev->pm.vblank_sync = true;  in rs600_irq_process()
812 				wake_up(&rdev->irq.vblank_queue);  in rs600_irq_process()
814 			if (atomic_read(&rdev->irq.pflip[1]))  in rs600_irq_process()
815 				radeon_crtc_handle_vblank(rdev, 1);  in rs600_irq_process()
817 		if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_process()
821 		if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {  in rs600_irq_process()
825 		if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {  in rs600_irq_process()
829 		status = rs600_irq_ack(rdev);  in rs600_irq_process()
832 		schedule_delayed_work(&rdev->hotplug_work, 0);  in rs600_irq_process()
834 		schedule_work(&rdev->audio_work);  in rs600_irq_process()
835 	if (rdev->msi_enabled) {  in rs600_irq_process()
836 		switch (rdev->family) {  in rs600_irq_process()
852 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)  in rs600_get_vblank_counter()  argument
860 int rs600_mc_wait_for_idle(struct radeon_device *rdev)  in rs600_mc_wait_for_idle()  argument
864 	for (i = 0; i < rdev->usec_timeout; i++) {  in rs600_mc_wait_for_idle()
872 static void rs600_gpu_init(struct radeon_device *rdev)  in rs600_gpu_init()  argument
874 	r420_pipes_init(rdev);  in rs600_gpu_init()
876 	if (rs600_mc_wait_for_idle(rdev))  in rs600_gpu_init()
877 		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");  in rs600_gpu_init()
880 static void rs600_mc_init(struct radeon_device *rdev)  in rs600_mc_init()  argument
884 	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);  in rs600_mc_init()
885 	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);  in rs600_mc_init()
886 	rdev->mc.vram_is_ddr = true;  in rs600_mc_init()
887 	rdev->mc.vram_width = 128;  in rs600_mc_init()
888 	rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);  in rs600_mc_init()
889 	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;  in rs600_mc_init()
890 	rdev->mc.visible_vram_size = rdev->mc.aper_size;  in rs600_mc_init()
891 	rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);  in rs600_mc_init()
894 	radeon_vram_location(rdev, &rdev->mc, base);  in rs600_mc_init()
895 	rdev->mc.gtt_base_align = 0;  in rs600_mc_init()
896 	radeon_gtt_location(rdev, &rdev->mc);  in rs600_mc_init()
897 	radeon_update_bandwidth_info(rdev);  in rs600_mc_init()
900 void rs600_bandwidth_update(struct radeon_device *rdev)  in rs600_bandwidth_update()  argument
907 	if (!rdev->mode_info.mode_config_initialized)  in rs600_bandwidth_update()
910 	radeon_update_display_priority(rdev);  in rs600_bandwidth_update()
912 	if (rdev->mode_info.crtcs[0]->base.enabled)  in rs600_bandwidth_update()
913 		mode0 = &rdev->mode_info.crtcs[0]->base.mode;  in rs600_bandwidth_update()
914 	if (rdev->mode_info.crtcs[1]->base.enabled)  in rs600_bandwidth_update()
915 		mode1 = &rdev->mode_info.crtcs[1]->base.mode;  in rs600_bandwidth_update()
917 	rs690_line_buffer_adjust(rdev, mode0, mode1);  in rs600_bandwidth_update()
919 	if (rdev->disp_priority == 2) {  in rs600_bandwidth_update()
931 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)  in rs600_mc_rreg()  argument
936 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);  in rs600_mc_rreg()
940 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);  in rs600_mc_rreg()
944 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)  in rs600_mc_wreg()  argument
948 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);  in rs600_mc_wreg()
952 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);  in rs600_mc_wreg()
955 void rs600_set_safe_registers(struct radeon_device *rdev)  in rs600_set_safe_registers()  argument
957 	rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;  in rs600_set_safe_registers()
958 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);  in rs600_set_safe_registers()
961 static void rs600_mc_program(struct radeon_device *rdev)  in rs600_mc_program()  argument
966 	rv515_mc_stop(rdev, &save);  in rs600_mc_program()
969 	if (rs600_mc_wait_for_idle(rdev))  in rs600_mc_program()
970 		dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");  in rs600_mc_program()
978 			S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |  in rs600_mc_program()
979 			S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));  in rs600_mc_program()
981 		S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));  in rs600_mc_program()
983 	rv515_mc_resume(rdev, &save);  in rs600_mc_program()
986 static int rs600_startup(struct radeon_device *rdev)  in rs600_startup()  argument
990 	rs600_mc_program(rdev);  in rs600_startup()
992 	rv515_clock_startup(rdev);  in rs600_startup()
994 	rs600_gpu_init(rdev);  in rs600_startup()
997 	r = rs600_gart_enable(rdev);  in rs600_startup()
1002 	r = radeon_wb_init(rdev);  in rs600_startup()
1006 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);  in rs600_startup()
1008 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);  in rs600_startup()
1013 	if (!rdev->irq.installed) {  in rs600_startup()
1014 		r = radeon_irq_kms_init(rdev);  in rs600_startup()
1019 	rs600_irq_set(rdev);  in rs600_startup()
1020 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);  in rs600_startup()
1022 	r = r100_cp_init(rdev, 1024 * 1024);  in rs600_startup()
1024 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);  in rs600_startup()
1028 	r = radeon_ib_pool_init(rdev);  in rs600_startup()
1030 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);  in rs600_startup()
1034 	r = radeon_audio_init(rdev);  in rs600_startup()
1036 		dev_err(rdev->dev, "failed initializing audio\n");  in rs600_startup()
1043 int rs600_resume(struct radeon_device *rdev)  in rs600_resume()  argument
1048 	rs600_gart_disable(rdev);  in rs600_resume()
1050 	rv515_clock_startup(rdev);  in rs600_resume()
1052 	if (radeon_asic_reset(rdev)) {  in rs600_resume()
1053 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in rs600_resume()
1058 	atom_asic_init(rdev->mode_info.atom_context);  in rs600_resume()
1060 	rv515_clock_startup(rdev);  in rs600_resume()
1062 	radeon_surface_init(rdev);  in rs600_resume()
1064 	rdev->accel_working = true;  in rs600_resume()
1065 	r = rs600_startup(rdev);  in rs600_resume()
1067 		rdev->accel_working = false;  in rs600_resume()
1072 int rs600_suspend(struct radeon_device *rdev)  in rs600_suspend()  argument
1074 	radeon_pm_suspend(rdev);  in rs600_suspend()
1075 	radeon_audio_fini(rdev);  in rs600_suspend()
1076 	r100_cp_disable(rdev);  in rs600_suspend()
1077 	radeon_wb_disable(rdev);  in rs600_suspend()
1078 	rs600_irq_disable(rdev);  in rs600_suspend()
1079 	rs600_gart_disable(rdev);  in rs600_suspend()
1083 void rs600_fini(struct radeon_device *rdev)  in rs600_fini()  argument
1085 	radeon_pm_fini(rdev);  in rs600_fini()
1086 	radeon_audio_fini(rdev);  in rs600_fini()
1087 	r100_cp_fini(rdev);  in rs600_fini()
1088 	radeon_wb_fini(rdev);  in rs600_fini()
1089 	radeon_ib_pool_fini(rdev);  in rs600_fini()
1090 	radeon_gem_fini(rdev);  in rs600_fini()
1091 	rs600_gart_fini(rdev);  in rs600_fini()
1092 	radeon_irq_kms_fini(rdev);  in rs600_fini()
1093 	radeon_fence_driver_fini(rdev);  in rs600_fini()
1094 	radeon_bo_fini(rdev);  in rs600_fini()
1095 	radeon_atombios_fini(rdev);  in rs600_fini()
1096 	kfree(rdev->bios);  in rs600_fini()
1097 	rdev->bios = NULL;  in rs600_fini()
1100 int rs600_init(struct radeon_device *rdev)  in rs600_init()  argument
1105 	rv515_vga_render_disable(rdev);  in rs600_init()
1107 	radeon_scratch_init(rdev);  in rs600_init()
1109 	radeon_surface_init(rdev);  in rs600_init()
1111 	r100_restore_sanity(rdev);  in rs600_init()
1113 	if (!radeon_get_bios(rdev)) {  in rs600_init()
1114 		if (ASIC_IS_AVIVO(rdev))  in rs600_init()
1117 	if (rdev->is_atom_bios) {  in rs600_init()
1118 		r = radeon_atombios_init(rdev);  in rs600_init()
1122 		dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");  in rs600_init()
1126 	if (radeon_asic_reset(rdev)) {  in rs600_init()
1127 		dev_warn(rdev->dev,  in rs600_init()
1133 	if (radeon_boot_test_post_card(rdev) == false)  in rs600_init()
1137 	radeon_get_clock_info(rdev->ddev);  in rs600_init()
1139 	rs600_mc_init(rdev);  in rs600_init()
1140 	r100_debugfs_rbbm_init(rdev);  in rs600_init()
1142 	radeon_fence_driver_init(rdev);  in rs600_init()
1144 	r = radeon_bo_init(rdev);  in rs600_init()
1147 	r = rs600_gart_init(rdev);  in rs600_init()
1150 	rs600_set_safe_registers(rdev);  in rs600_init()
1153 	radeon_pm_init(rdev);  in rs600_init()
1155 	rdev->accel_working = true;  in rs600_init()
1156 	r = rs600_startup(rdev);  in rs600_init()
1159 		dev_err(rdev->dev, "Disabling GPU acceleration\n");  in rs600_init()
1160 		r100_cp_fini(rdev);  in rs600_init()
1161 		radeon_wb_fini(rdev);  in rs600_init()
1162 		radeon_ib_pool_fini(rdev);  in rs600_init()
1163 		rs600_gart_fini(rdev);  in rs600_init()
1164 		radeon_irq_kms_fini(rdev);  in rs600_init()
1165 		rdev->accel_working = false;  in rs600_init()