Lines Matching refs:rdev
36 int r520_mc_wait_for_idle(struct radeon_device *rdev) in r520_mc_wait_for_idle() argument
41 for (i = 0; i < rdev->usec_timeout; i++) { in r520_mc_wait_for_idle()
52 static void r520_gpu_init(struct radeon_device *rdev) in r520_gpu_init() argument
56 rv515_vga_render_disable(rdev); in r520_gpu_init()
78 if (rdev->family == CHIP_RV530) { in r520_gpu_init()
81 r420_pipes_init(rdev); in r520_gpu_init()
88 if (r520_mc_wait_for_idle(rdev)) { in r520_gpu_init()
93 static void r520_vram_get_type(struct radeon_device *rdev) in r520_vram_get_type() argument
97 rdev->mc.vram_width = 128; in r520_vram_get_type()
98 rdev->mc.vram_is_ddr = true; in r520_vram_get_type()
102 rdev->mc.vram_width = 32; in r520_vram_get_type()
105 rdev->mc.vram_width = 64; in r520_vram_get_type()
108 rdev->mc.vram_width = 128; in r520_vram_get_type()
111 rdev->mc.vram_width = 256; in r520_vram_get_type()
114 rdev->mc.vram_width = 128; in r520_vram_get_type()
118 rdev->mc.vram_width *= 2; in r520_vram_get_type()
121 static void r520_mc_init(struct radeon_device *rdev) in r520_mc_init() argument
124 r520_vram_get_type(rdev); in r520_mc_init()
125 r100_vram_init_sizes(rdev); in r520_mc_init()
126 radeon_vram_location(rdev, &rdev->mc, 0); in r520_mc_init()
127 rdev->mc.gtt_base_align = 0; in r520_mc_init()
128 if (!(rdev->flags & RADEON_IS_AGP)) in r520_mc_init()
129 radeon_gtt_location(rdev, &rdev->mc); in r520_mc_init()
130 radeon_update_bandwidth_info(rdev); in r520_mc_init()
133 static void r520_mc_program(struct radeon_device *rdev) in r520_mc_program() argument
138 rv515_mc_stop(rdev, &save); in r520_mc_program()
141 if (r520_mc_wait_for_idle(rdev)) in r520_mc_program()
142 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in r520_mc_program()
144 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); in r520_mc_program()
147 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in r520_mc_program()
148 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); in r520_mc_program()
150 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in r520_mc_program()
151 if (rdev->flags & RADEON_IS_AGP) { in r520_mc_program()
153 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | in r520_mc_program()
154 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); in r520_mc_program()
155 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r520_mc_program()
157 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); in r520_mc_program()
164 rv515_mc_resume(rdev, &save); in r520_mc_program()
167 static int r520_startup(struct radeon_device *rdev) in r520_startup() argument
171 r520_mc_program(rdev); in r520_startup()
173 rv515_clock_startup(rdev); in r520_startup()
175 r520_gpu_init(rdev); in r520_startup()
178 if (rdev->flags & RADEON_IS_PCIE) { in r520_startup()
179 r = rv370_pcie_gart_enable(rdev); in r520_startup()
185 r = radeon_wb_init(rdev); in r520_startup()
189 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r520_startup()
191 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r520_startup()
196 if (!rdev->irq.installed) { in r520_startup()
197 r = radeon_irq_kms_init(rdev); in r520_startup()
202 rs600_irq_set(rdev); in r520_startup()
203 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r520_startup()
205 r = r100_cp_init(rdev, 1024 * 1024); in r520_startup()
207 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r520_startup()
211 r = radeon_ib_pool_init(rdev); in r520_startup()
213 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r520_startup()
220 int r520_resume(struct radeon_device *rdev) in r520_resume() argument
225 if (rdev->flags & RADEON_IS_PCIE) in r520_resume()
226 rv370_pcie_gart_disable(rdev); in r520_resume()
228 rv515_clock_startup(rdev); in r520_resume()
230 if (radeon_asic_reset(rdev)) { in r520_resume()
231 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r520_resume()
236 atom_asic_init(rdev->mode_info.atom_context); in r520_resume()
238 rv515_clock_startup(rdev); in r520_resume()
240 radeon_surface_init(rdev); in r520_resume()
242 rdev->accel_working = true; in r520_resume()
243 r = r520_startup(rdev); in r520_resume()
245 rdev->accel_working = false; in r520_resume()
250 int r520_init(struct radeon_device *rdev) in r520_init() argument
255 radeon_scratch_init(rdev); in r520_init()
257 radeon_surface_init(rdev); in r520_init()
259 r100_restore_sanity(rdev); in r520_init()
262 if (!radeon_get_bios(rdev)) { in r520_init()
263 if (ASIC_IS_AVIVO(rdev)) in r520_init()
266 if (rdev->is_atom_bios) { in r520_init()
267 r = radeon_atombios_init(rdev); in r520_init()
271 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); in r520_init()
275 if (radeon_asic_reset(rdev)) { in r520_init()
276 dev_warn(rdev->dev, in r520_init()
282 if (radeon_boot_test_post_card(rdev) == false) in r520_init()
285 if (!radeon_card_posted(rdev) && rdev->bios) { in r520_init()
287 atom_asic_init(rdev->mode_info.atom_context); in r520_init()
290 radeon_get_clock_info(rdev->ddev); in r520_init()
292 if (rdev->flags & RADEON_IS_AGP) { in r520_init()
293 r = radeon_agp_init(rdev); in r520_init()
295 radeon_agp_disable(rdev); in r520_init()
299 r520_mc_init(rdev); in r520_init()
300 rv515_debugfs(rdev); in r520_init()
302 radeon_fence_driver_init(rdev); in r520_init()
304 r = radeon_bo_init(rdev); in r520_init()
307 r = rv370_pcie_gart_init(rdev); in r520_init()
310 rv515_set_safe_registers(rdev); in r520_init()
313 radeon_pm_init(rdev); in r520_init()
315 rdev->accel_working = true; in r520_init()
316 r = r520_startup(rdev); in r520_init()
319 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r520_init()
320 r100_cp_fini(rdev); in r520_init()
321 radeon_wb_fini(rdev); in r520_init()
322 radeon_ib_pool_fini(rdev); in r520_init()
323 radeon_irq_kms_fini(rdev); in r520_init()
324 rv370_pcie_gart_fini(rdev); in r520_init()
325 radeon_agp_fini(rdev); in r520_init()
326 rdev->accel_working = false; in r520_init()