630 	struct radeon_bo_list *reloc;  in r300_packet0_check()  local
664 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
671 		track->cb[i].robj = reloc->robj;  in r300_packet0_check()
674 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
677 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
684 		track->zb.robj = reloc->robj;  in r300_packet0_check()
687 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
706 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
716 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
718 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
720 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
722 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
725 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
729 		track->textures[i].robj = reloc->robj;  in r300_packet0_check()
779 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
787 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
789 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
791 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
864 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
872 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
874 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
876 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
1079 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1086 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1121 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1128 		track->aa.robj = reloc->robj;  in r300_packet0_check()
1131 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1175 	struct radeon_bo_list *reloc;  in r300_packet3_check()  local
1191 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet3_check()
1197 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r300_packet3_check()
1198 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);  in r300_packet3_check()