60 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)  in rv370_pcie_rreg()  argument
65 	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);  in rv370_pcie_rreg()
66 	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));  in rv370_pcie_rreg()
68 	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);  in rv370_pcie_rreg()
72 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)  in rv370_pcie_wreg()  argument
76 	spin_lock_irqsave(&rdev->pcie_idx_lock, flags);  in rv370_pcie_wreg()
77 	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));  in rv370_pcie_wreg()
79 	spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);  in rv370_pcie_wreg()
85 static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
87 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)  in rv370_pcie_gart_tlb_flush()  argument
119 void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,  in rv370_pcie_gart_set_page()  argument
122 	void __iomem *ptr = rdev->gart.ptr;  in rv370_pcie_gart_set_page()
130 int rv370_pcie_gart_init(struct radeon_device *rdev)  in rv370_pcie_gart_init()  argument
134 	if (rdev->gart.robj) {  in rv370_pcie_gart_init()
139 	r = radeon_gart_init(rdev);  in rv370_pcie_gart_init()
142 	rv370_debugfs_pcie_gart_info_init(rdev);  in rv370_pcie_gart_init()
144 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;  in rv370_pcie_gart_init()
145 	rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;  in rv370_pcie_gart_init()
146 	rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;  in rv370_pcie_gart_init()
147 	rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;  in rv370_pcie_gart_init()
148 	return radeon_gart_table_vram_alloc(rdev);  in rv370_pcie_gart_init()
151 int rv370_pcie_gart_enable(struct radeon_device *rdev)  in rv370_pcie_gart_enable()  argument
157 	if (rdev->gart.robj == NULL) {  in rv370_pcie_gart_enable()
158 		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");  in rv370_pcie_gart_enable()
161 	r = radeon_gart_table_vram_pin(rdev);  in rv370_pcie_gart_enable()
167 	WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);  in rv370_pcie_gart_enable()
168 	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;  in rv370_pcie_gart_enable()
172 	table_addr = rdev->gart.table_addr;  in rv370_pcie_gart_enable()
175 	WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);  in rv370_pcie_gart_enable()
183 	rv370_pcie_gart_tlb_flush(rdev);  in rv370_pcie_gart_enable()
185 		 (unsigned)(rdev->mc.gtt_size >> 20),  in rv370_pcie_gart_enable()
187 	rdev->gart.ready = true;  in rv370_pcie_gart_enable()
191 void rv370_pcie_gart_disable(struct radeon_device *rdev)  in rv370_pcie_gart_disable()  argument
202 	radeon_gart_table_vram_unpin(rdev);  in rv370_pcie_gart_disable()
205 void rv370_pcie_gart_fini(struct radeon_device *rdev)  in rv370_pcie_gart_fini()  argument
207 	radeon_gart_fini(rdev);  in rv370_pcie_gart_fini()
208 	rv370_pcie_gart_disable(rdev);  in rv370_pcie_gart_fini()
209 	radeon_gart_table_vram_free(rdev);  in rv370_pcie_gart_fini()
212 void r300_fence_ring_emit(struct radeon_device *rdev,  in r300_fence_ring_emit()  argument
215 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in r300_fence_ring_emit()
235 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl |  in r300_fence_ring_emit()
238 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl);  in r300_fence_ring_emit()
240 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r300_fence_ring_emit()
246 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)  in r300_ring_start()  argument
253 	switch(rdev->num_gb_pipes) {  in r300_ring_start()
269 	r = radeon_ring_lock(rdev, ring, 64);  in r300_ring_start()
333 	radeon_ring_unlock_commit(rdev, ring, false);  in r300_ring_start()
336 static void r300_errata(struct radeon_device *rdev)  in r300_errata()  argument
338 	rdev->pll_errata = 0;  in r300_errata()
340 	if (rdev->family == CHIP_R300 &&  in r300_errata()
342 		rdev->pll_errata |= CHIP_ERRATA_R300_CG;  in r300_errata()
346 int r300_mc_wait_for_idle(struct radeon_device *rdev)  in r300_mc_wait_for_idle()  argument
351 	for (i = 0; i < rdev->usec_timeout; i++) {  in r300_mc_wait_for_idle()
362 static void r300_gpu_init(struct radeon_device *rdev)  in r300_gpu_init()  argument
366 	if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||  in r300_gpu_init()
367 	    (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {  in r300_gpu_init()
369 		rdev->num_gb_pipes = 2;  in r300_gpu_init()
372 		rdev->num_gb_pipes = 1;  in r300_gpu_init()
374 	rdev->num_z_pipes = 1;  in r300_gpu_init()
376 	switch (rdev->num_gb_pipes) {  in r300_gpu_init()
393 	if (r100_gui_wait_for_idle(rdev)) {  in r300_gpu_init()
404 	if (r100_gui_wait_for_idle(rdev)) {  in r300_gpu_init()
407 	if (r300_mc_wait_for_idle(rdev)) {  in r300_gpu_init()
411 		 rdev->num_gb_pipes, rdev->num_z_pipes);  in r300_gpu_init()
414 int r300_asic_reset(struct radeon_device *rdev, bool hard)  in r300_asic_reset()  argument
424 	r100_mc_stop(rdev, &save);  in r300_asic_reset()
426 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
435 	pci_save_state(rdev->pdev);  in r300_asic_reset()
437 	r100_bm_disable(rdev);  in r300_asic_reset()
445 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
457 	dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);  in r300_asic_reset()
459 	pci_restore_state(rdev->pdev);  in r300_asic_reset()
460 	r100_enable_bm(rdev);  in r300_asic_reset()
463 		dev_err(rdev->dev, "failed to reset GPU\n");  in r300_asic_reset()
466 		dev_info(rdev->dev, "GPU reset succeed\n");  in r300_asic_reset()
467 	r100_mc_resume(rdev, &save);  in r300_asic_reset()
474 void r300_mc_init(struct radeon_device *rdev)  in r300_mc_init()  argument
480 	rdev->mc.vram_is_ddr = true;  in r300_mc_init()
484 	case 0: rdev->mc.vram_width = 64; break;  in r300_mc_init()
485 	case 1: rdev->mc.vram_width = 128; break;  in r300_mc_init()
486 	case 2: rdev->mc.vram_width = 256; break;  in r300_mc_init()
487 	default:  rdev->mc.vram_width = 128; break;  in r300_mc_init()
489 	r100_vram_init_sizes(rdev);  in r300_mc_init()
490 	base = rdev->mc.aper_base;  in r300_mc_init()
491 	if (rdev->flags & RADEON_IS_IGP)  in r300_mc_init()
493 	radeon_vram_location(rdev, &rdev->mc, base);  in r300_mc_init()
494 	rdev->mc.gtt_base_align = 0;  in r300_mc_init()
495 	if (!(rdev->flags & RADEON_IS_AGP))  in r300_mc_init()
496 		radeon_gtt_location(rdev, &rdev->mc);  in r300_mc_init()
497 	radeon_update_bandwidth_info(rdev);  in r300_mc_init()
500 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)  in rv370_set_pcie_lanes()  argument
504 	if (rdev->flags & RADEON_IS_IGP)  in rv370_set_pcie_lanes()
507 	if (!(rdev->flags & RADEON_IS_PCIE))  in rv370_set_pcie_lanes()
559 int rv370_get_pcie_lanes(struct radeon_device *rdev)  in rv370_get_pcie_lanes()  argument
563 	if (rdev->flags & RADEON_IS_IGP)  in rv370_get_pcie_lanes()
566 	if (!(rdev->flags & RADEON_IS_PCIE))  in rv370_get_pcie_lanes()
593 	struct radeon_device *rdev = (struct radeon_device *)m->private;  in rv370_debugfs_pcie_gart_info_show()  local
616 static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)  in rv370_debugfs_pcie_gart_info_init()  argument
619 	struct dentry *root = rdev->ddev->primary->debugfs_root;  in rv370_debugfs_pcie_gart_info_init()
621 	debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev,  in rv370_debugfs_pcie_gart_info_init()
747 		if (p->rdev->family < CHIP_RV515)  in r300_packet0_check()
754 		if (p->rdev->family < CHIP_RV515) {  in r300_packet0_check()
763 		    p->rdev->cmask_filp != p->filp) {  in r300_packet0_check()
813 			if (p->rdev->family < CHIP_RV515) {  in r300_packet0_check()
963 			if (p->rdev->family < CHIP_R420) {  in r300_packet0_check()
1030 		if (p->rdev->family >= CHIP_RV515) {  in r300_packet0_check()
1097 		if (p->rdev->hyperz_filp != p->filp) {  in r300_packet0_check()
1107 		if (p->rdev->hyperz_filp != p->filp) {  in r300_packet0_check()
1145 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1149 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1152 		if (p->rdev->family >= CHIP_RV350)  in r300_packet0_check()
1158 		if (p->rdev->family == CHIP_RV530)  in r300_packet0_check()
1214 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1229 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1236 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1243 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1250 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1257 		r = r100_cs_track_check(p->rdev, track);  in r300_packet3_check()
1264 		if (p->rdev->hyperz_filp != p->filp)  in r300_packet3_check()
1268 		if (p->rdev->cmask_filp != p->filp)  in r300_packet3_check()
1289 	r100_cs_track_clear(p->rdev, track);  in r300_cs_parse()
1300 						  p->rdev->config.r300.reg_safe_bm,  in r300_cs_parse()
1301 						  p->rdev->config.r300.reg_safe_bm_size,  in r300_cs_parse()
1320 void r300_set_reg_safe(struct radeon_device *rdev)  in r300_set_reg_safe()  argument
1322 	rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;  in r300_set_reg_safe()
1323 	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);  in r300_set_reg_safe()
1326 void r300_mc_program(struct radeon_device *rdev)  in r300_mc_program()  argument
1330 	r100_debugfs_mc_info_init(rdev);  in r300_mc_program()
1333 	r100_mc_stop(rdev, &save);  in r300_mc_program()
1334 	if (rdev->flags & RADEON_IS_AGP) {  in r300_mc_program()
1336 			S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |  in r300_mc_program()
1337 			S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));  in r300_mc_program()
1338 		WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));  in r300_mc_program()
1340 			upper_32_bits(rdev->mc.agp_base) & 0xff);  in r300_mc_program()
1347 	if (r300_mc_wait_for_idle(rdev))  in r300_mc_program()
1351 		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |  in r300_mc_program()
1352 		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));  in r300_mc_program()
1353 	r100_mc_resume(rdev, &save);  in r300_mc_program()
1356 void r300_clock_startup(struct radeon_device *rdev)  in r300_clock_startup()  argument
1361 		radeon_legacy_set_clock_gating(rdev, 1);  in r300_clock_startup()
1365 	if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))  in r300_clock_startup()
1370 static int r300_startup(struct radeon_device *rdev)  in r300_startup()  argument
1375 	r100_set_common_regs(rdev);  in r300_startup()
1377 	r300_mc_program(rdev);  in r300_startup()
1379 	r300_clock_startup(rdev);  in r300_startup()
1381 	r300_gpu_init(rdev);  in r300_startup()
1384 	if (rdev->flags & RADEON_IS_PCIE) {  in r300_startup()
1385 		r = rv370_pcie_gart_enable(rdev);  in r300_startup()
1390 	if (rdev->family == CHIP_R300 ||  in r300_startup()
1391 	    rdev->family == CHIP_R350 ||  in r300_startup()
1392 	    rdev->family == CHIP_RV350)  in r300_startup()
1393 		r100_enable_bm(rdev);  in r300_startup()
1395 	if (rdev->flags & RADEON_IS_PCI) {  in r300_startup()
1396 		r = r100_pci_gart_enable(rdev);  in r300_startup()
1402 	r = radeon_wb_init(rdev);  in r300_startup()
1406 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);  in r300_startup()
1408 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);  in r300_startup()
1413 	if (!rdev->irq.installed) {  in r300_startup()
1414 		r = radeon_irq_kms_init(rdev);  in r300_startup()
1419 	r100_irq_set(rdev);  in r300_startup()
1420 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);  in r300_startup()
1422 	r = r100_cp_init(rdev, 1024 * 1024);  in r300_startup()
1424 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);  in r300_startup()
1428 	r = radeon_ib_pool_init(rdev);  in r300_startup()
1430 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);  in r300_startup()
1437 int r300_resume(struct radeon_device *rdev)  in r300_resume()  argument
1442 	if (rdev->flags & RADEON_IS_PCIE)  in r300_resume()
1443 		rv370_pcie_gart_disable(rdev);  in r300_resume()
1444 	if (rdev->flags & RADEON_IS_PCI)  in r300_resume()
1445 		r100_pci_gart_disable(rdev);  in r300_resume()
1447 	r300_clock_startup(rdev);  in r300_resume()
1449 	if (radeon_asic_reset(rdev)) {  in r300_resume()
1450 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",  in r300_resume()
1455 	radeon_combios_asic_init(rdev->ddev);  in r300_resume()
1457 	r300_clock_startup(rdev);  in r300_resume()
1459 	radeon_surface_init(rdev);  in r300_resume()
1461 	rdev->accel_working = true;  in r300_resume()
1462 	r = r300_startup(rdev);  in r300_resume()
1464 		rdev->accel_working = false;  in r300_resume()
1469 int r300_suspend(struct radeon_device *rdev)  in r300_suspend()  argument
1471 	radeon_pm_suspend(rdev);  in r300_suspend()
1472 	r100_cp_disable(rdev);  in r300_suspend()
1473 	radeon_wb_disable(rdev);  in r300_suspend()
1474 	r100_irq_disable(rdev);  in r300_suspend()
1475 	if (rdev->flags & RADEON_IS_PCIE)  in r300_suspend()
1476 		rv370_pcie_gart_disable(rdev);  in r300_suspend()
1477 	if (rdev->flags & RADEON_IS_PCI)  in r300_suspend()
1478 		r100_pci_gart_disable(rdev);  in r300_suspend()
1482 void r300_fini(struct radeon_device *rdev)  in r300_fini()  argument
1484 	radeon_pm_fini(rdev);  in r300_fini()
1485 	r100_cp_fini(rdev);  in r300_fini()
1486 	radeon_wb_fini(rdev);  in r300_fini()
1487 	radeon_ib_pool_fini(rdev);  in r300_fini()
1488 	radeon_gem_fini(rdev);  in r300_fini()
1489 	if (rdev->flags & RADEON_IS_PCIE)  in r300_fini()
1490 		rv370_pcie_gart_fini(rdev);  in r300_fini()
1491 	if (rdev->flags & RADEON_IS_PCI)  in r300_fini()
1492 		r100_pci_gart_fini(rdev);  in r300_fini()
1493 	radeon_agp_fini(rdev);  in r300_fini()
1494 	radeon_irq_kms_fini(rdev);  in r300_fini()
1495 	radeon_fence_driver_fini(rdev);  in r300_fini()
1496 	radeon_bo_fini(rdev);  in r300_fini()
1497 	radeon_atombios_fini(rdev);  in r300_fini()
1498 	kfree(rdev->bios);  in r300_fini()
1499 	rdev->bios = NULL;  in r300_fini()
1502 int r300_init(struct radeon_device *rdev)  in r300_init()  argument
1507 	r100_vga_render_disable(rdev);  in r300_init()
1509 	radeon_scratch_init(rdev);  in r300_init()
1511 	radeon_surface_init(rdev);  in r300_init()
1514 	r100_restore_sanity(rdev);  in r300_init()
1516 	if (!radeon_get_bios(rdev)) {  in r300_init()
1517 		if (ASIC_IS_AVIVO(rdev))  in r300_init()
1520 	if (rdev->is_atom_bios) {  in r300_init()
1521 		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");  in r300_init()
1524 		r = radeon_combios_init(rdev);  in r300_init()
1529 	if (radeon_asic_reset(rdev)) {  in r300_init()
1530 		dev_warn(rdev->dev,  in r300_init()
1536 	if (radeon_boot_test_post_card(rdev) == false)  in r300_init()
1539 	r300_errata(rdev);  in r300_init()
1541 	radeon_get_clock_info(rdev->ddev);  in r300_init()
1543 	if (rdev->flags & RADEON_IS_AGP) {  in r300_init()
1544 		r = radeon_agp_init(rdev);  in r300_init()
1546 			radeon_agp_disable(rdev);  in r300_init()
1550 	r300_mc_init(rdev);  in r300_init()
1552 	radeon_fence_driver_init(rdev);  in r300_init()
1554 	r = radeon_bo_init(rdev);  in r300_init()
1557 	if (rdev->flags & RADEON_IS_PCIE) {  in r300_init()
1558 		r = rv370_pcie_gart_init(rdev);  in r300_init()
1562 	if (rdev->flags & RADEON_IS_PCI) {  in r300_init()
1563 		r = r100_pci_gart_init(rdev);  in r300_init()
1567 	r300_set_reg_safe(rdev);  in r300_init()
1570 	radeon_pm_init(rdev);  in r300_init()
1572 	rdev->accel_working = true;  in r300_init()
1573 	r = r300_startup(rdev);  in r300_init()
1576 		dev_err(rdev->dev, "Disabling GPU acceleration\n");  in r300_init()
1577 		r100_cp_fini(rdev);  in r300_init()
1578 		radeon_wb_fini(rdev);  in r300_init()
1579 		radeon_ib_pool_fini(rdev);  in r300_init()
1580 		radeon_irq_kms_fini(rdev);  in r300_init()
1581 		if (rdev->flags & RADEON_IS_PCIE)  in r300_init()
1582 			rv370_pcie_gart_fini(rdev);  in r300_init()
1583 		if (rdev->flags & RADEON_IS_PCI)  in r300_init()
1584 			r100_pci_gart_fini(rdev);  in r300_init()
1585 		radeon_agp_fini(rdev);  in r300_init()
1586 		rdev->accel_working = false;  in r300_init()