Lines Matching refs:performance_levels
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
812 if (ps->performance_levels[i].vddc > max_limits->vddc) in ni_apply_state_adjust_rules()
813 ps->performance_levels[i].vddc = max_limits->vddc; in ni_apply_state_adjust_rules()
814 if (ps->performance_levels[i].vddci > max_limits->vddci) in ni_apply_state_adjust_rules()
815 ps->performance_levels[i].vddci = max_limits->vddci; in ni_apply_state_adjust_rules()
823 ps->performance_levels[0].mclk = in ni_apply_state_adjust_rules()
824 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()
825 ps->performance_levels[0].vddci = in ni_apply_state_adjust_rules()
826 ps->performance_levels[ps->performance_level_count - 1].vddci; in ni_apply_state_adjust_rules()
830 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules()
831 &ps->performance_levels[0].mclk); in ni_apply_state_adjust_rules()
834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
836 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in ni_apply_state_adjust_rules()
837 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in ni_apply_state_adjust_rules()
842 mclk = ps->performance_levels[0].mclk; in ni_apply_state_adjust_rules()
843 vddci = ps->performance_levels[0].vddci; in ni_apply_state_adjust_rules()
845 if (mclk < ps->performance_levels[i].mclk) in ni_apply_state_adjust_rules()
846 mclk = ps->performance_levels[i].mclk; in ni_apply_state_adjust_rules()
847 if (vddci < ps->performance_levels[i].vddci) in ni_apply_state_adjust_rules()
848 vddci = ps->performance_levels[i].vddci; in ni_apply_state_adjust_rules()
851 ps->performance_levels[i].mclk = mclk; in ni_apply_state_adjust_rules()
852 ps->performance_levels[i].vddci = vddci; in ni_apply_state_adjust_rules()
856 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in ni_apply_state_adjust_rules()
857 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in ni_apply_state_adjust_rules()
858 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in ni_apply_state_adjust_rules()
859 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in ni_apply_state_adjust_rules()
865 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
866 &ps->performance_levels[i].mclk); in ni_apply_state_adjust_rules()
870 &ps->performance_levels[i]); in ni_apply_state_adjust_rules()
874 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
875 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
877 ps->performance_levels[i].mclk, in ni_apply_state_adjust_rules()
878 max_limits->vddci, &ps->performance_levels[i].vddci); in ni_apply_state_adjust_rules()
880 ps->performance_levels[i].mclk, in ni_apply_state_adjust_rules()
881 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
884 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
890 &ps->performance_levels[i].vddc, in ni_apply_state_adjust_rules()
891 &ps->performance_levels[i].vddci); in ni_apply_state_adjust_rules()
896 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in ni_apply_state_adjust_rules()
899 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) in ni_apply_state_adjust_rules()
900 ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2; in ni_apply_state_adjust_rules()
1401 state->performance_levels[state->performance_level_count - 2].vddc, in ni_calculate_power_boost_limit()
1411 state->performance_levels[state->performance_level_count - 1].vddc, in ni_calculate_power_boost_limit()
1646 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); in ni_do_program_memory_timing_parameters()
1707 cpu_to_be32(initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1722 cpu_to_be32(initial_state->performance_levels[0].sclk); in ni_populate_smc_initial_state()
1729 initial_state->performance_levels[0].vddc, in ni_populate_smc_initial_state()
1746 initial_state->performance_levels[0].vddci, in ni_populate_smc_initial_state()
1764 initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state()
1766 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in ni_populate_smc_initial_state()
2418 state->performance_levels[i + 1].sclk, in ni_populate_smc_t()
2419 state->performance_levels[i].sclk, in ni_populate_smc_t()
2426 state->performance_levels[i + 1].sclk, in ni_populate_smc_t()
2427 state->performance_levels[i].sclk, in ni_populate_smc_t()
2502 prev_sclk = state->performance_levels[i-1].sclk; in ni_populate_power_containment_values()
2503 max_sclk = state->performance_levels[i].sclk; in ni_populate_power_containment_values()
2517 if (min_sclk < state->performance_levels[0].sclk) in ni_populate_power_containment_values()
2518 min_sclk = state->performance_levels[0].sclk; in ni_populate_power_containment_values()
2575 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in ni_populate_sq_ramping_values()
2632 u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100; in ni_convert_power_state_to_smc()
2643 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i], in ni_convert_power_state_to_smc()
2653 (state->performance_levels[i].sclk < threshold) ? in ni_convert_power_state_to_smc()
2986 &state->performance_levels[i], in ni_convert_mc_reg_table_to_smc()
3006 ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], in ni_populate_mc_reg_table()
3518 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3519 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3536 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3537 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
3926 struct rv7xx_pl *pl = &ps->performance_levels[index]; in ni_parse_pplib_clock_info()
3948 if (ps->performance_levels[0].flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in ni_parse_pplib_clock_info()
4292 pl = &ps->performance_levels[i]; in ni_dpm_print_power_state()
4317 pl = &ps->performance_levels[current_index]; in ni_dpm_debugfs_print_current_performance_level()
4337 pl = &ps->performance_levels[current_index]; in ni_dpm_get_current_sclk()
4355 pl = &ps->performance_levels[current_index]; in ni_dpm_get_current_mclk()
4366 return requested_state->performance_levels[0].sclk; in ni_dpm_get_sclk()
4368 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in ni_dpm_get_sclk()
4377 return requested_state->performance_levels[0].mclk; in ni_dpm_get_mclk()
4379 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in ni_dpm_get_mclk()