Lines Matching refs:rdev
47 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) in tn_smc_rreg() argument
52 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
59 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in tn_smc_wreg() argument
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
443 static void ni_init_golden_registers(struct radeon_device *rdev) in ni_init_golden_registers() argument
445 switch (rdev->family) { in ni_init_golden_registers()
447 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
450 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
455 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
456 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
457 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
458 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
459 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
460 (rdev->pdev->device == 0x9906) || in ni_init_golden_registers()
461 (rdev->pdev->device == 0x9907) || in ni_init_golden_registers()
462 (rdev->pdev->device == 0x9908) || in ni_init_golden_registers()
463 (rdev->pdev->device == 0x9909) || in ni_init_golden_registers()
464 (rdev->pdev->device == 0x990A) || in ni_init_golden_registers()
465 (rdev->pdev->device == 0x990B) || in ni_init_golden_registers()
466 (rdev->pdev->device == 0x990C) || in ni_init_golden_registers()
467 (rdev->pdev->device == 0x990D) || in ni_init_golden_registers()
468 (rdev->pdev->device == 0x990E) || in ni_init_golden_registers()
469 (rdev->pdev->device == 0x990F) || in ni_init_golden_registers()
470 (rdev->pdev->device == 0x9910) || in ni_init_golden_registers()
471 (rdev->pdev->device == 0x9913) || in ni_init_golden_registers()
472 (rdev->pdev->device == 0x9917) || in ni_init_golden_registers()
473 (rdev->pdev->device == 0x9918)) { in ni_init_golden_registers()
474 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
477 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
481 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
484 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
624 int ni_mc_load_microcode(struct radeon_device *rdev) in ni_mc_load_microcode() argument
631 if (!rdev->mc_fw) in ni_mc_load_microcode()
634 switch (rdev->family) { in ni_mc_load_microcode()
677 fw_data = (const __be32 *)rdev->mc_fw->data; in ni_mc_load_microcode()
687 for (i = 0; i < rdev->usec_timeout; i++) { in ni_mc_load_microcode()
700 int ni_init_microcode(struct radeon_device *rdev) in ni_init_microcode() argument
711 switch (rdev->family) { in ni_init_microcode()
763 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in ni_init_microcode()
766 if (rdev->pfp_fw->size != pfp_req_size) { in ni_init_microcode()
768 rdev->pfp_fw->size, fw_name); in ni_init_microcode()
774 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in ni_init_microcode()
777 if (rdev->me_fw->size != me_req_size) { in ni_init_microcode()
779 rdev->me_fw->size, fw_name); in ni_init_microcode()
784 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in ni_init_microcode()
787 if (rdev->rlc_fw->size != rlc_req_size) { in ni_init_microcode()
789 rdev->rlc_fw->size, fw_name); in ni_init_microcode()
794 if (!(rdev->flags & RADEON_IS_IGP)) { in ni_init_microcode()
796 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in ni_init_microcode()
799 if (rdev->mc_fw->size != mc_req_size) { in ni_init_microcode()
801 rdev->mc_fw->size, fw_name); in ni_init_microcode()
806 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { in ni_init_microcode()
808 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in ni_init_microcode()
811 release_firmware(rdev->smc_fw); in ni_init_microcode()
812 rdev->smc_fw = NULL; in ni_init_microcode()
814 } else if (rdev->smc_fw->size != smc_req_size) { in ni_init_microcode()
816 rdev->mc_fw->size, fw_name); in ni_init_microcode()
826 release_firmware(rdev->pfp_fw); in ni_init_microcode()
827 rdev->pfp_fw = NULL; in ni_init_microcode()
828 release_firmware(rdev->me_fw); in ni_init_microcode()
829 rdev->me_fw = NULL; in ni_init_microcode()
830 release_firmware(rdev->rlc_fw); in ni_init_microcode()
831 rdev->rlc_fw = NULL; in ni_init_microcode()
832 release_firmware(rdev->mc_fw); in ni_init_microcode()
833 rdev->mc_fw = NULL; in ni_init_microcode()
848 int cayman_get_allowed_info_register(struct radeon_device *rdev, in cayman_get_allowed_info_register() argument
867 int tn_get_temp(struct radeon_device *rdev) in tn_get_temp() argument
878 static void cayman_gpu_init(struct radeon_device *rdev) in cayman_gpu_init() argument
891 switch (rdev->family) { in cayman_gpu_init()
893 rdev->config.cayman.max_shader_engines = 2; in cayman_gpu_init()
894 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
895 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()
896 rdev->config.cayman.max_simds_per_se = 12; in cayman_gpu_init()
897 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()
898 rdev->config.cayman.max_texture_channel_caches = 8; in cayman_gpu_init()
899 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
900 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
901 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
902 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
903 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
904 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
905 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
906 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
907 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
908 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
910 rdev->config.cayman.sc_prim_fifo_size = 0x100; in cayman_gpu_init()
911 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
912 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
917 rdev->config.cayman.max_shader_engines = 1; in cayman_gpu_init()
918 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
919 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
920 if ((rdev->pdev->device == 0x9900) || in cayman_gpu_init()
921 (rdev->pdev->device == 0x9901) || in cayman_gpu_init()
922 (rdev->pdev->device == 0x9905) || in cayman_gpu_init()
923 (rdev->pdev->device == 0x9906) || in cayman_gpu_init()
924 (rdev->pdev->device == 0x9907) || in cayman_gpu_init()
925 (rdev->pdev->device == 0x9908) || in cayman_gpu_init()
926 (rdev->pdev->device == 0x9909) || in cayman_gpu_init()
927 (rdev->pdev->device == 0x990B) || in cayman_gpu_init()
928 (rdev->pdev->device == 0x990C) || in cayman_gpu_init()
929 (rdev->pdev->device == 0x990F) || in cayman_gpu_init()
930 (rdev->pdev->device == 0x9910) || in cayman_gpu_init()
931 (rdev->pdev->device == 0x9917) || in cayman_gpu_init()
932 (rdev->pdev->device == 0x9999) || in cayman_gpu_init()
933 (rdev->pdev->device == 0x999C)) { in cayman_gpu_init()
934 rdev->config.cayman.max_simds_per_se = 6; in cayman_gpu_init()
935 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
936 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
937 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
938 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
939 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
940 } else if ((rdev->pdev->device == 0x9903) || in cayman_gpu_init()
941 (rdev->pdev->device == 0x9904) || in cayman_gpu_init()
942 (rdev->pdev->device == 0x990A) || in cayman_gpu_init()
943 (rdev->pdev->device == 0x990D) || in cayman_gpu_init()
944 (rdev->pdev->device == 0x990E) || in cayman_gpu_init()
945 (rdev->pdev->device == 0x9913) || in cayman_gpu_init()
946 (rdev->pdev->device == 0x9918) || in cayman_gpu_init()
947 (rdev->pdev->device == 0x999D)) { in cayman_gpu_init()
948 rdev->config.cayman.max_simds_per_se = 4; in cayman_gpu_init()
949 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
950 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
951 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
952 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
953 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
954 } else if ((rdev->pdev->device == 0x9919) || in cayman_gpu_init()
955 (rdev->pdev->device == 0x9990) || in cayman_gpu_init()
956 (rdev->pdev->device == 0x9991) || in cayman_gpu_init()
957 (rdev->pdev->device == 0x9994) || in cayman_gpu_init()
958 (rdev->pdev->device == 0x9995) || in cayman_gpu_init()
959 (rdev->pdev->device == 0x9996) || in cayman_gpu_init()
960 (rdev->pdev->device == 0x999A) || in cayman_gpu_init()
961 (rdev->pdev->device == 0x99A0)) { in cayman_gpu_init()
962 rdev->config.cayman.max_simds_per_se = 3; in cayman_gpu_init()
963 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
964 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
965 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
966 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
967 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
969 rdev->config.cayman.max_simds_per_se = 2; in cayman_gpu_init()
970 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
971 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
972 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
973 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
974 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
976 rdev->config.cayman.max_texture_channel_caches = 2; in cayman_gpu_init()
977 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
978 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
979 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
980 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
981 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
982 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
984 rdev->config.cayman.sc_prim_fifo_size = 0x40; in cayman_gpu_init()
985 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
986 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
1004 evergreen_fix_pci_max_read_req_size(rdev); in cayman_gpu_init()
1010 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in cayman_gpu_init()
1011 if (rdev->config.cayman.mem_row_size_in_kb > 4) in cayman_gpu_init()
1012 rdev->config.cayman.mem_row_size_in_kb = 4; in cayman_gpu_init()
1014 rdev->config.cayman.shader_engine_tile_size = 32; in cayman_gpu_init()
1015 rdev->config.cayman.num_gpus = 1; in cayman_gpu_init()
1016 rdev->config.cayman.multi_gpu_tile_size = 64; in cayman_gpu_init()
1019 rdev->config.cayman.num_tile_pipes = (1 << tmp); in cayman_gpu_init()
1021 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; in cayman_gpu_init()
1023 rdev->config.cayman.num_shader_engines = tmp + 1; in cayman_gpu_init()
1025 rdev->config.cayman.num_gpus = tmp + 1; in cayman_gpu_init()
1027 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; in cayman_gpu_init()
1029 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; in cayman_gpu_init()
1039 rdev->config.cayman.tile_config = 0; in cayman_gpu_init()
1040 switch (rdev->config.cayman.num_tile_pipes) { in cayman_gpu_init()
1043 rdev->config.cayman.tile_config |= (0 << 0); in cayman_gpu_init()
1046 rdev->config.cayman.tile_config |= (1 << 0); in cayman_gpu_init()
1049 rdev->config.cayman.tile_config |= (2 << 0); in cayman_gpu_init()
1052 rdev->config.cayman.tile_config |= (3 << 0); in cayman_gpu_init()
1057 if (rdev->flags & RADEON_IS_IGP) in cayman_gpu_init()
1058 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1062 rdev->config.cayman.tile_config |= 0 << 4; in cayman_gpu_init()
1065 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1069 rdev->config.cayman.tile_config |= 2 << 4; in cayman_gpu_init()
1073 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1075 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1079 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { in cayman_gpu_init()
1091 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1095 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1099 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { in cayman_gpu_init()
1105 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in cayman_gpu_init()
1109 rdev->config.cayman.active_simds = hweight32(~tmp); in cayman_gpu_init()
1116 if (ASIC_IS_DCE6(rdev)) in cayman_gpu_init()
1125 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()
1126 (rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_init()
1136 tmp = r6xx_remap_render_backend(rdev, tmp, in cayman_gpu_init()
1137 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
1138 rdev->config.cayman.max_shader_engines, in cayman_gpu_init()
1141 rdev->config.cayman.backend_map = tmp; in cayman_gpu_init()
1145 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) in cayman_gpu_init()
1167 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); in cayman_gpu_init()
1183 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1… in cayman_gpu_init()
1184 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | in cayman_gpu_init()
1185 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); in cayman_gpu_init()
1187 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | in cayman_gpu_init()
1188 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | in cayman_gpu_init()
1189 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); in cayman_gpu_init()
1196 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | in cayman_gpu_init()
1239 if (rdev->family == CHIP_ARUBA) { in cayman_gpu_init()
1252 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) in cayman_pcie_gart_tlb_flush() argument
1261 static int cayman_pcie_gart_enable(struct radeon_device *rdev) in cayman_pcie_gart_enable() argument
1265 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1266 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in cayman_pcie_gart_enable()
1269 r = radeon_gart_table_vram_pin(rdev); in cayman_pcie_gart_enable()
1292 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cayman_pcie_gart_enable()
1293 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cayman_pcie_gart_enable()
1294 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1296 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1313 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1315 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1320 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1337 cayman_pcie_gart_tlb_flush(rdev); in cayman_pcie_gart_enable()
1339 (unsigned)(rdev->mc.gtt_size >> 20), in cayman_pcie_gart_enable()
1340 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1341 rdev->gart.ready = true; in cayman_pcie_gart_enable()
1345 static void cayman_pcie_gart_disable(struct radeon_device *rdev) in cayman_pcie_gart_disable() argument
1350 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
1369 radeon_gart_table_vram_unpin(rdev); in cayman_pcie_gart_disable()
1372 static void cayman_pcie_gart_fini(struct radeon_device *rdev) in cayman_pcie_gart_fini() argument
1374 cayman_pcie_gart_disable(rdev); in cayman_pcie_gart_fini()
1375 radeon_gart_table_vram_free(rdev); in cayman_pcie_gart_fini()
1376 radeon_gart_fini(rdev); in cayman_pcie_gart_fini()
1379 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, in cayman_cp_int_cntl_setup() argument
1389 void cayman_fence_ring_emit(struct radeon_device *rdev, in cayman_fence_ring_emit() argument
1392 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit()
1393 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1412 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in cayman_ring_ib_execute() argument
1414 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute()
1448 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) in cayman_cp_enable() argument
1453 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_enable()
1454 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_cp_enable()
1457 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1461 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, in cayman_gfx_get_rptr() argument
1466 if (rdev->wb.enabled) in cayman_gfx_get_rptr()
1467 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1480 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, in cayman_gfx_get_wptr() argument
1495 void cayman_gfx_set_wptr(struct radeon_device *rdev, in cayman_gfx_set_wptr() argument
1510 static int cayman_cp_load_microcode(struct radeon_device *rdev) in cayman_cp_load_microcode() argument
1515 if (!rdev->me_fw || !rdev->pfp_fw) in cayman_cp_load_microcode()
1518 cayman_cp_enable(rdev, false); in cayman_cp_load_microcode()
1520 fw_data = (const __be32 *)rdev->pfp_fw->data; in cayman_cp_load_microcode()
1526 fw_data = (const __be32 *)rdev->me_fw->data; in cayman_cp_load_microcode()
1537 static int cayman_cp_start(struct radeon_device *rdev) in cayman_cp_start() argument
1539 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start()
1542 r = radeon_ring_lock(rdev, ring, 7); in cayman_cp_start()
1550 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1554 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1556 cayman_cp_enable(rdev, true); in cayman_cp_start()
1558 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); in cayman_cp_start()
1596 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1603 static void cayman_cp_fini(struct radeon_device *rdev) in cayman_cp_fini() argument
1605 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini()
1606 cayman_cp_enable(rdev, false); in cayman_cp_fini()
1607 radeon_ring_fini(rdev, ring); in cayman_cp_fini()
1608 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1611 static int cayman_cp_resume(struct radeon_device *rdev) in cayman_cp_resume() argument
1672 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1680 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1689 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1696 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1702 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1714 cayman_cp_start(rdev); in cayman_cp_resume()
1715 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1716 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1717 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1719 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1721 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1722 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1723 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1727 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_resume()
1728 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in cayman_cp_resume()
1733 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) in cayman_gpu_check_soft_reset() argument
1794 if (evergreen_is_display_hung(rdev)) in cayman_gpu_check_soft_reset()
1811 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in cayman_gpu_soft_reset() argument
1820 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cayman_gpu_soft_reset()
1822 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1823 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1825 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1827 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1829 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1851 evergreen_mc_stop(rdev, &save); in cayman_gpu_soft_reset()
1852 if (evergreen_mc_wait_for_idle(rdev)) { in cayman_gpu_soft_reset()
1853 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cayman_gpu_soft_reset()
1901 if (!(rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_soft_reset()
1909 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1923 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1937 evergreen_mc_resume(rdev, &save); in cayman_gpu_soft_reset()
1940 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1943 int cayman_asic_reset(struct radeon_device *rdev, bool hard) in cayman_asic_reset() argument
1948 evergreen_gpu_pci_config_reset(rdev); in cayman_asic_reset()
1952 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1955 r600_set_bios_scratch_engine_hung(rdev, true); in cayman_asic_reset()
1957 cayman_gpu_soft_reset(rdev, reset_mask); in cayman_asic_reset()
1959 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1962 evergreen_gpu_pci_config_reset(rdev); in cayman_asic_reset()
1964 r600_set_bios_scratch_engine_hung(rdev, false); in cayman_asic_reset()
1978 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cayman_gfx_is_lockup() argument
1980 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_gfx_is_lockup()
1985 radeon_ring_lockup_update(rdev, ring); in cayman_gfx_is_lockup()
1988 return radeon_ring_test_lockup(rdev, ring); in cayman_gfx_is_lockup()
1991 static void cayman_uvd_init(struct radeon_device *rdev) in cayman_uvd_init() argument
1995 if (!rdev->has_uvd) in cayman_uvd_init()
1998 r = radeon_uvd_init(rdev); in cayman_uvd_init()
2000 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in cayman_uvd_init()
2007 rdev->has_uvd = false; in cayman_uvd_init()
2010 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in cayman_uvd_init()
2011 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in cayman_uvd_init()
2014 static void cayman_uvd_start(struct radeon_device *rdev) in cayman_uvd_start() argument
2018 if (!rdev->has_uvd) in cayman_uvd_start()
2021 r = uvd_v2_2_resume(rdev); in cayman_uvd_start()
2023 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in cayman_uvd_start()
2026 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in cayman_uvd_start()
2028 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in cayman_uvd_start()
2034 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_uvd_start()
2037 static void cayman_uvd_resume(struct radeon_device *rdev) in cayman_uvd_resume() argument
2042 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in cayman_uvd_resume()
2045 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_uvd_resume()
2046 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in cayman_uvd_resume()
2048 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in cayman_uvd_resume()
2051 r = uvd_v1_0_init(rdev); in cayman_uvd_resume()
2053 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in cayman_uvd_resume()
2058 static void cayman_vce_init(struct radeon_device *rdev) in cayman_vce_init() argument
2063 if (!rdev->has_vce) in cayman_vce_init()
2066 r = radeon_vce_init(rdev); in cayman_vce_init()
2068 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); in cayman_vce_init()
2075 rdev->has_vce = false; in cayman_vce_init()
2078 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; in cayman_vce_init()
2079 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); in cayman_vce_init()
2080 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; in cayman_vce_init()
2081 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); in cayman_vce_init()
2084 static void cayman_vce_start(struct radeon_device *rdev) in cayman_vce_start() argument
2088 if (!rdev->has_vce) in cayman_vce_start()
2091 r = radeon_vce_resume(rdev); in cayman_vce_start()
2093 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2096 r = vce_v1_0_resume(rdev); in cayman_vce_start()
2098 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2101 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX); in cayman_vce_start()
2103 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); in cayman_vce_start()
2106 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX); in cayman_vce_start()
2108 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); in cayman_vce_start()
2114 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_vce_start()
2115 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_vce_start()
2118 static void cayman_vce_resume(struct radeon_device *rdev) in cayman_vce_resume() argument
2123 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in cayman_vce_resume()
2126 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_vce_resume()
2127 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2129 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2132 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_vce_resume()
2133 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2135 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2138 r = vce_v1_0_init(rdev); in cayman_vce_resume()
2140 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); in cayman_vce_resume()
2145 static int cayman_startup(struct radeon_device *rdev) in cayman_startup() argument
2147 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup()
2151 evergreen_pcie_gen2_enable(rdev); in cayman_startup()
2153 evergreen_program_aspm(rdev); in cayman_startup()
2156 r = r600_vram_scratch_init(rdev); in cayman_startup()
2160 evergreen_mc_program(rdev); in cayman_startup()
2162 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { in cayman_startup()
2163 r = ni_mc_load_microcode(rdev); in cayman_startup()
2170 r = cayman_pcie_gart_enable(rdev); in cayman_startup()
2173 cayman_gpu_init(rdev); in cayman_startup()
2176 if (rdev->flags & RADEON_IS_IGP) { in cayman_startup()
2177 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2178 rdev->rlc.reg_list_size = in cayman_startup()
2180 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
2181 r = sumo_rlc_init(rdev); in cayman_startup()
2189 r = radeon_wb_init(rdev); in cayman_startup()
2193 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in cayman_startup()
2195 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2199 cayman_uvd_start(rdev); in cayman_startup()
2200 cayman_vce_start(rdev); in cayman_startup()
2202 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in cayman_startup()
2204 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2208 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); in cayman_startup()
2210 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2214 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in cayman_startup()
2216 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2220 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); in cayman_startup()
2222 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2227 if (!rdev->irq.installed) { in cayman_startup()
2228 r = radeon_irq_kms_init(rdev); in cayman_startup()
2233 r = r600_irq_init(rdev); in cayman_startup()
2236 radeon_irq_kms_fini(rdev); in cayman_startup()
2239 evergreen_irq_set(rdev); in cayman_startup()
2241 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2246 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2247 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2252 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2253 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2258 r = cayman_cp_load_microcode(rdev); in cayman_startup()
2261 r = cayman_cp_resume(rdev); in cayman_startup()
2265 r = cayman_dma_resume(rdev); in cayman_startup()
2269 cayman_uvd_resume(rdev); in cayman_startup()
2270 cayman_vce_resume(rdev); in cayman_startup()
2272 r = radeon_ib_pool_init(rdev); in cayman_startup()
2274 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in cayman_startup()
2278 r = radeon_vm_manager_init(rdev); in cayman_startup()
2280 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in cayman_startup()
2284 r = radeon_audio_init(rdev); in cayman_startup()
2291 int cayman_resume(struct radeon_device *rdev) in cayman_resume() argument
2300 atom_asic_init(rdev->mode_info.atom_context); in cayman_resume()
2303 ni_init_golden_registers(rdev); in cayman_resume()
2305 if (rdev->pm.pm_method == PM_METHOD_DPM) in cayman_resume()
2306 radeon_pm_resume(rdev); in cayman_resume()
2308 rdev->accel_working = true; in cayman_resume()
2309 r = cayman_startup(rdev); in cayman_resume()
2312 rdev->accel_working = false; in cayman_resume()
2318 int cayman_suspend(struct radeon_device *rdev) in cayman_suspend() argument
2320 radeon_pm_suspend(rdev); in cayman_suspend()
2321 radeon_audio_fini(rdev); in cayman_suspend()
2322 radeon_vm_manager_fini(rdev); in cayman_suspend()
2323 cayman_cp_enable(rdev, false); in cayman_suspend()
2324 cayman_dma_stop(rdev); in cayman_suspend()
2325 if (rdev->has_uvd) { in cayman_suspend()
2326 radeon_uvd_suspend(rdev); in cayman_suspend()
2327 uvd_v1_0_fini(rdev); in cayman_suspend()
2329 evergreen_irq_suspend(rdev); in cayman_suspend()
2330 radeon_wb_disable(rdev); in cayman_suspend()
2331 cayman_pcie_gart_disable(rdev); in cayman_suspend()
2341 int cayman_init(struct radeon_device *rdev) in cayman_init() argument
2343 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init()
2347 if (!radeon_get_bios(rdev)) { in cayman_init()
2348 if (ASIC_IS_AVIVO(rdev)) in cayman_init()
2352 if (!rdev->is_atom_bios) { in cayman_init()
2353 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in cayman_init()
2356 r = radeon_atombios_init(rdev); in cayman_init()
2361 if (!radeon_card_posted(rdev)) { in cayman_init()
2362 if (!rdev->bios) { in cayman_init()
2363 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in cayman_init()
2367 atom_asic_init(rdev->mode_info.atom_context); in cayman_init()
2370 ni_init_golden_registers(rdev); in cayman_init()
2372 r600_scratch_init(rdev); in cayman_init()
2374 radeon_surface_init(rdev); in cayman_init()
2376 radeon_get_clock_info(rdev->ddev); in cayman_init()
2378 radeon_fence_driver_init(rdev); in cayman_init()
2380 r = evergreen_mc_init(rdev); in cayman_init()
2384 r = radeon_bo_init(rdev); in cayman_init()
2388 if (rdev->flags & RADEON_IS_IGP) { in cayman_init()
2389 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in cayman_init()
2390 r = ni_init_microcode(rdev); in cayman_init()
2397 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in cayman_init()
2398 r = ni_init_microcode(rdev); in cayman_init()
2407 radeon_pm_init(rdev); in cayman_init()
2410 r600_ring_init(rdev, ring, 1024 * 1024); in cayman_init()
2412 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2414 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2416 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2418 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2420 cayman_uvd_init(rdev); in cayman_init()
2421 cayman_vce_init(rdev); in cayman_init()
2423 rdev->ih.ring_obj = NULL; in cayman_init()
2424 r600_ih_ring_init(rdev, 64 * 1024); in cayman_init()
2426 r = r600_pcie_gart_init(rdev); in cayman_init()
2430 rdev->accel_working = true; in cayman_init()
2431 r = cayman_startup(rdev); in cayman_init()
2433 dev_err(rdev->dev, "disabling GPU acceleration\n"); in cayman_init()
2434 cayman_cp_fini(rdev); in cayman_init()
2435 cayman_dma_fini(rdev); in cayman_init()
2436 r600_irq_fini(rdev); in cayman_init()
2437 if (rdev->flags & RADEON_IS_IGP) in cayman_init()
2438 sumo_rlc_fini(rdev); in cayman_init()
2439 radeon_wb_fini(rdev); in cayman_init()
2440 radeon_ib_pool_fini(rdev); in cayman_init()
2441 radeon_vm_manager_fini(rdev); in cayman_init()
2442 radeon_irq_kms_fini(rdev); in cayman_init()
2443 cayman_pcie_gart_fini(rdev); in cayman_init()
2444 rdev->accel_working = false; in cayman_init()
2454 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in cayman_init()
2462 void cayman_fini(struct radeon_device *rdev) in cayman_fini() argument
2464 radeon_pm_fini(rdev); in cayman_fini()
2465 cayman_cp_fini(rdev); in cayman_fini()
2466 cayman_dma_fini(rdev); in cayman_fini()
2467 r600_irq_fini(rdev); in cayman_fini()
2468 if (rdev->flags & RADEON_IS_IGP) in cayman_fini()
2469 sumo_rlc_fini(rdev); in cayman_fini()
2470 radeon_wb_fini(rdev); in cayman_fini()
2471 radeon_vm_manager_fini(rdev); in cayman_fini()
2472 radeon_ib_pool_fini(rdev); in cayman_fini()
2473 radeon_irq_kms_fini(rdev); in cayman_fini()
2474 uvd_v1_0_fini(rdev); in cayman_fini()
2475 radeon_uvd_fini(rdev); in cayman_fini()
2476 if (rdev->has_vce) in cayman_fini()
2477 radeon_vce_fini(rdev); in cayman_fini()
2478 cayman_pcie_gart_fini(rdev); in cayman_fini()
2479 r600_vram_scratch_fini(rdev); in cayman_fini()
2480 radeon_gem_fini(rdev); in cayman_fini()
2481 radeon_fence_driver_fini(rdev); in cayman_fini()
2482 radeon_bo_fini(rdev); in cayman_fini()
2483 radeon_atombios_fini(rdev); in cayman_fini()
2484 kfree(rdev->bios); in cayman_fini()
2485 rdev->bios = NULL; in cayman_fini()
2491 int cayman_vm_init(struct radeon_device *rdev) in cayman_vm_init() argument
2494 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2496 if (rdev->flags & RADEON_IS_IGP) { in cayman_vm_init()
2499 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2501 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
2505 void cayman_vm_fini(struct radeon_device *rdev) in cayman_vm_fini() argument
2518 void cayman_vm_decode_fault(struct radeon_device *rdev, in cayman_vm_decode_fault() argument
2676 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cayman_vm_flush() argument
2705 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
2710 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in tn_set_vce_clocks()