Lines Matching refs:WREG32
62 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
73 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
74 WREG32(EVERGREEN_CG_IND_DATA, (v)); in eg_cg_wreg()
84 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
95 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
96 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); in eg_pif_phy0_wreg()
106 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
117 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
118 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); in eg_pif_phy1_wreg()
1183 WREG32(CG_SCRATCH1, cg_scratch); in sumo_set_uvd_clocks()
1344 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1422 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in evergreen_page_flip()
1425 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1428 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1430 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1686 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()
1711 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()
1788 WREG32(DC_HPDx_CONTROL(hpd), tmp); in evergreen_hpd_init()
1817 WREG32(DC_HPDx_CONTROL(hpd), 0); in evergreen_hpd_fini()
1869 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); in evergreen_line_buffer_adjust()
1872 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
2290 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2291 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2298 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2299 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2303 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); in evergreen_program_watermarks()
2306 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in evergreen_program_watermarks()
2307 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in evergreen_program_watermarks()
2381 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in evergreen_pcie_gart_tlb_flush()
2383 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); in evergreen_pcie_gart_tlb_flush()
2412 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2415 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_enable()
2416 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2423 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2424 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2425 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2427 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2428 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2429 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2434 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2436 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2437 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2438 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2439 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2440 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in evergreen_pcie_gart_enable()
2441 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in evergreen_pcie_gart_enable()
2442 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
2443 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
2445 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in evergreen_pcie_gart_enable()
2447 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_enable()
2462 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_pcie_gart_disable()
2463 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_pcie_gart_disable()
2466 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_disable()
2468 WREG32(VM_L2_CNTL2, 0); in evergreen_pcie_gart_disable()
2469 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2472 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2473 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2474 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2475 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2476 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2477 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2478 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_disable()
2495 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
2498 WREG32(VM_L2_CNTL2, 0); in evergreen_agp_enable()
2499 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
2505 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2506 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2507 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2508 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2509 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2510 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2511 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_agp_enable()
2512 WREG32(VM_CONTEXT0_CNTL, 0); in evergreen_agp_enable()
2513 WREG32(VM_CONTEXT1_CNTL, 0); in evergreen_agp_enable()
2646 WREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2662 WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl); in evergreen_blank_dp_output()
2677 WREG32(VGA_RENDER_CONTROL, 0); in evergreen_mc_stop()
2688 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2690 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2691 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2697 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2699 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2700 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2722 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2725 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2726 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
2739 WREG32(BIF_FB_EN, 0); in evergreen_mc_stop()
2742 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in evergreen_mc_stop()
2753 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop()
2758 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_stop()
2771 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in evergreen_mc_resume()
2773 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], in evergreen_mc_resume()
2775 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], in evergreen_mc_resume()
2777 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], in evergreen_mc_resume()
2782 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2783 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2792 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2797 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2802 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_resume()
2816 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); in evergreen_mc_resume()
2818 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in evergreen_mc_resume()
2825 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_resume()
2826 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2827 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_resume()
2831 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_resume()
2832 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2833 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_resume()
2846 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); in evergreen_mc_resume()
2848 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); in evergreen_mc_resume()
2860 WREG32((0x2c14 + j), 0x00000000); in evergreen_mc_program()
2861 WREG32((0x2c18 + j), 0x00000000); in evergreen_mc_program()
2862 WREG32((0x2c1c + j), 0x00000000); in evergreen_mc_program()
2863 WREG32((0x2c20 + j), 0x00000000); in evergreen_mc_program()
2864 WREG32((0x2c24 + j), 0x00000000); in evergreen_mc_program()
2866 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in evergreen_mc_program()
2873 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in evergreen_mc_program()
2878 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2880 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2884 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2886 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2890 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in evergreen_mc_program()
2892 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in evergreen_mc_program()
2895 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
2903 WREG32(MC_FUS_VM_FB_OFFSET, tmp); in evergreen_mc_program()
2907 WREG32(MC_VM_FB_LOCATION, tmp); in evergreen_mc_program()
2908 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in evergreen_mc_program()
2909 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in evergreen_mc_program()
2910 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in evergreen_mc_program()
2912 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in evergreen_mc_program()
2913 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in evergreen_mc_program()
2914 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in evergreen_mc_program()
2916 WREG32(MC_VM_AGP_BASE, 0); in evergreen_mc_program()
2917 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in evergreen_mc_program()
2918 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in evergreen_mc_program()
2976 WREG32(CP_RB_CNTL, in evergreen_cp_load_microcode()
2983 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
2985 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_cp_load_microcode()
2986 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
2989 WREG32(CP_ME_RAM_WADDR, 0); in evergreen_cp_load_microcode()
2991 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in evergreen_cp_load_microcode()
2993 WREG32(CP_PFP_UCODE_ADDR, 0); in evergreen_cp_load_microcode()
2994 WREG32(CP_ME_RAM_WADDR, 0); in evergreen_cp_load_microcode()
2995 WREG32(CP_ME_RAM_RADDR, 0); in evergreen_cp_load_microcode()
3020 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3073 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | in evergreen_cp_resume()
3081 WREG32(GRBM_SOFT_RESET, 0); in evergreen_cp_resume()
3090 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3091 WREG32(CP_SEM_WAIT_TIMER, 0x0); in evergreen_cp_resume()
3092 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in evergreen_cp_resume()
3095 WREG32(CP_RB_WPTR_DELAY, 0); in evergreen_cp_resume()
3098 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in evergreen_cp_resume()
3099 WREG32(CP_RB_RPTR_WR, 0); in evergreen_cp_resume()
3101 WREG32(CP_RB_WPTR, ring->wptr); in evergreen_cp_resume()
3104 WREG32(CP_RB_RPTR_ADDR, in evergreen_cp_resume()
3106 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3107 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
3110 WREG32(SCRATCH_UMSK, 0xff); in evergreen_cp_resume()
3113 WREG32(SCRATCH_UMSK, 0); in evergreen_cp_resume()
3117 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3119 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in evergreen_cp_resume()
3120 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); in evergreen_cp_resume()
3389 WREG32((0x2c14 + j), 0x00000000); in evergreen_gpu_init()
3390 WREG32((0x2c18 + j), 0x00000000); in evergreen_gpu_init()
3391 WREG32((0x2c1c + j), 0x00000000); in evergreen_gpu_init()
3392 WREG32((0x2c20 + j), 0x00000000); in evergreen_gpu_init()
3393 WREG32((0x2c24 + j), 0x00000000); in evergreen_gpu_init()
3396 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in evergreen_gpu_init()
3397 WREG32(SRBM_INT_CNTL, 0x1); in evergreen_gpu_init()
3398 WREG32(SRBM_INT_ACK, 0x1); in evergreen_gpu_init()
3467 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3468 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3488 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3489 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3497 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
3498 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
3500 WREG32(GB_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3501 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3502 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3503 WREG32(DMA_TILING_CONFIG, gb_addr_config); in evergreen_gpu_init()
3504 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3505 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3506 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in evergreen_gpu_init()
3523 WREG32(GB_BACKEND_MAP, tmp); in evergreen_gpu_init()
3525 WREG32(CGTS_SYS_TCC_DISABLE, 0); in evergreen_gpu_init()
3526 WREG32(CGTS_TCC_DISABLE, 0); in evergreen_gpu_init()
3527 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); in evergreen_gpu_init()
3528 WREG32(CGTS_USER_TCC_DISABLE, 0); in evergreen_gpu_init()
3531 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in evergreen_gpu_init()
3534 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); in evergreen_gpu_init()
3536 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | in evergreen_gpu_init()
3543 WREG32(SX_DEBUG_1, sx_debug_1); in evergreen_gpu_init()
3549 WREG32(SMX_DC_CTL0, smx_dc_ctl0); in evergreen_gpu_init()
3552 WREG32(SMX_SAR_CTL0, 0x00010000); in evergreen_gpu_init()
3554 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) … in evergreen_gpu_init()
3558 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | in evergreen_gpu_init()
3562 WREG32(VGT_NUM_INSTANCES, 1); in evergreen_gpu_init()
3563 WREG32(SPI_CONFIG_CNTL, 0); in evergreen_gpu_init()
3564 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in evergreen_gpu_init()
3565 WREG32(CP_PERFMON_CNTL, 0); in evergreen_gpu_init()
3567 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | in evergreen_gpu_init()
3633 WREG32(SQ_CONFIG, sq_config); in evergreen_gpu_init()
3634 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); in evergreen_gpu_init()
3635 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); in evergreen_gpu_init()
3636 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); in evergreen_gpu_init()
3637 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in evergreen_gpu_init()
3638 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); in evergreen_gpu_init()
3639 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); in evergreen_gpu_init()
3640 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); in evergreen_gpu_init()
3641 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); in evergreen_gpu_init()
3642 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); in evergreen_gpu_init()
3643 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); in evergreen_gpu_init()
3645 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in evergreen_gpu_init()
3661 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); in evergreen_gpu_init()
3663 WREG32(VGT_GS_VERTEX_REUSE, 16); in evergreen_gpu_init()
3664 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); in evergreen_gpu_init()
3665 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in evergreen_gpu_init()
3667 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in evergreen_gpu_init()
3668 WREG32(VGT_OUT_DEALLOC_CNTL, 16); in evergreen_gpu_init()
3670 WREG32(CB_PERF_CTR0_SEL_0, 0); in evergreen_gpu_init()
3671 WREG32(CB_PERF_CTR0_SEL_1, 0); in evergreen_gpu_init()
3672 WREG32(CB_PERF_CTR1_SEL_0, 0); in evergreen_gpu_init()
3673 WREG32(CB_PERF_CTR1_SEL_1, 0); in evergreen_gpu_init()
3674 WREG32(CB_PERF_CTR2_SEL_0, 0); in evergreen_gpu_init()
3675 WREG32(CB_PERF_CTR2_SEL_1, 0); in evergreen_gpu_init()
3676 WREG32(CB_PERF_CTR3_SEL_0, 0); in evergreen_gpu_init()
3677 WREG32(CB_PERF_CTR3_SEL_1, 0); in evergreen_gpu_init()
3680 WREG32(CB_COLOR0_BASE, 0); in evergreen_gpu_init()
3681 WREG32(CB_COLOR1_BASE, 0); in evergreen_gpu_init()
3682 WREG32(CB_COLOR2_BASE, 0); in evergreen_gpu_init()
3683 WREG32(CB_COLOR3_BASE, 0); in evergreen_gpu_init()
3684 WREG32(CB_COLOR4_BASE, 0); in evergreen_gpu_init()
3685 WREG32(CB_COLOR5_BASE, 0); in evergreen_gpu_init()
3686 WREG32(CB_COLOR6_BASE, 0); in evergreen_gpu_init()
3687 WREG32(CB_COLOR7_BASE, 0); in evergreen_gpu_init()
3688 WREG32(CB_COLOR8_BASE, 0); in evergreen_gpu_init()
3689 WREG32(CB_COLOR9_BASE, 0); in evergreen_gpu_init()
3690 WREG32(CB_COLOR10_BASE, 0); in evergreen_gpu_init()
3691 WREG32(CB_COLOR11_BASE, 0); in evergreen_gpu_init()
3695 WREG32(i, 0); in evergreen_gpu_init()
3697 WREG32(i, 0); in evergreen_gpu_init()
3701 WREG32(HDP_MISC_CNTL, tmp); in evergreen_gpu_init()
3704 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in evergreen_gpu_init()
3706 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in evergreen_gpu_init()
3911 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
3917 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
3978 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
3984 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
3992 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
3998 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4021 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
4026 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
4380 WREG32(RLC_CNTL, mask); in evergreen_rlc_start()
4393 WREG32(RLC_HB_CNTL, 0); in evergreen_rlc_resume()
4404 WREG32(TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK, always_on_bitmap); in evergreen_rlc_resume()
4405 WREG32(TN_RLC_LB_PARAMS, 0x00601004); in evergreen_rlc_resume()
4406 WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff); in evergreen_rlc_resume()
4407 WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000); in evergreen_rlc_resume()
4408 WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000); in evergreen_rlc_resume()
4411 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in evergreen_rlc_resume()
4412 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in evergreen_rlc_resume()
4414 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4415 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
4417 WREG32(RLC_HB_BASE, 0); in evergreen_rlc_resume()
4418 WREG32(RLC_HB_RPTR, 0); in evergreen_rlc_resume()
4419 WREG32(RLC_HB_WPTR, 0); in evergreen_rlc_resume()
4420 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in evergreen_rlc_resume()
4421 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in evergreen_rlc_resume()
4423 WREG32(RLC_MC_CNTL, 0); in evergreen_rlc_resume()
4424 WREG32(RLC_UCODE_CNTL, 0); in evergreen_rlc_resume()
4429 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4430 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4434 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4435 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4439 WREG32(RLC_UCODE_ADDR, i); in evergreen_rlc_resume()
4440 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in evergreen_rlc_resume()
4443 WREG32(RLC_UCODE_ADDR, 0); in evergreen_rlc_resume()
4471 WREG32(CAYMAN_DMA1_CNTL, tmp); in evergreen_disable_interrupt_state()
4473 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in evergreen_disable_interrupt_state()
4475 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4476 WREG32(GRBM_INT_CNTL, 0); in evergreen_disable_interrupt_state()
4477 WREG32(SRBM_INT_CNTL, 0); in evergreen_disable_interrupt_state()
4479 WREG32(INT_MASK + crtc_offsets[i], 0); in evergreen_disable_interrupt_state()
4481 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in evergreen_disable_interrupt_state()
4485 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); in evergreen_disable_interrupt_state()
4486 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); in evergreen_disable_interrupt_state()
4568 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
4570 WREG32(DMA_CNTL, dma_cntl); in evergreen_irq_set()
4573 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1); in evergreen_irq_set()
4575 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in evergreen_irq_set()
4586 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in evergreen_irq_set()
4596 WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int); in evergreen_irq_set()
4598 WREG32(CG_THERMAL_INT, thermal_int); in evergreen_irq_set()
4632 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in evergreen_irq_ack()
4638 WREG32(VBLANK_STATUS + crtc_offsets[j], in evergreen_irq_ack()
4641 WREG32(VLINE_STATUS + crtc_offsets[j], in evergreen_irq_ack()
4698 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()
4838 WREG32(SRBM_INT_ACK, 0x1); in evergreen_irq_process()
4913 WREG32(IH_RB_RPTR, rptr); in evergreen_irq_process()