91 		WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);  in cypress_enable_dynamic_pcie_gen2()
93 		WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);  in cypress_enable_dynamic_pcie_gen2()
102 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
103 		WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
104 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
109 	WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
140 			WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);  in cypress_gfx_clock_gating_enable()
142 		WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);  in cypress_gfx_clock_gating_enable()
144 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);  in cypress_gfx_clock_gating_enable()
145 		WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);  in cypress_gfx_clock_gating_enable()
146 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);  in cypress_gfx_clock_gating_enable()
150 			WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);  in cypress_gfx_clock_gating_enable()
197 			WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
198 			WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
199 			WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
200 			WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
201 			WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
202 			WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
203 			WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
204 			WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);  in cypress_mg_clock_gating_enable()
226 			WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);  in cypress_enable_spread_spectrum()
229 			WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);  in cypress_enable_spread_spectrum()
231 		WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);  in cypress_enable_spread_spectrum()
232 		WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);  in cypress_enable_spread_spectrum()
233 		WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);  in cypress_enable_spread_spectrum()
234 		WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);  in cypress_enable_spread_spectrum()
240 	WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);  in cypress_start_dpm()
247 		WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);  in cypress_enable_sclk_control()
249 		WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);  in cypress_enable_sclk_control()
256 		WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);  in cypress_enable_mclk_control()
258 		WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);  in cypress_enable_mclk_control()
1101 			WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);  in cypress_wait_for_mc_sequencer()
1102 			WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);  in cypress_wait_for_mc_sequencer()
1104 			WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);  in cypress_wait_for_mc_sequencer()
1105 			WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);  in cypress_wait_for_mc_sequencer()