806 			if (ps->performance_levels[i].mclk > max_limits->mclk)  in ci_apply_state_adjust_rules()
807 				ps->performance_levels[i].mclk = max_limits->mclk;  in ci_apply_state_adjust_rules()
808 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in ci_apply_state_adjust_rules()
809 				ps->performance_levels[i].sclk = max_limits->sclk;  in ci_apply_state_adjust_rules()
816 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in ci_apply_state_adjust_rules()
817 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
819 		mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
820 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
830 	ps->performance_levels[0].sclk = sclk;  in ci_apply_state_adjust_rules()
831 	ps->performance_levels[0].mclk = mclk;  in ci_apply_state_adjust_rules()
833 	if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)  in ci_apply_state_adjust_rules()
834 		ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
837 		if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)  in ci_apply_state_adjust_rules()
838 			ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;  in ci_apply_state_adjust_rules()
840 		if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)  in ci_apply_state_adjust_rules()
841 			ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
2556 		    boot_state->performance_levels[0].sclk) {  in ci_populate_smc_initial_state()
2564 		    boot_state->performance_levels[0].mclk) {  in ci_populate_smc_initial_state()
3727 				  state->performance_levels[0].sclk,  in ci_trim_dpm_states()
3728 				  state->performance_levels[high_limit_count].sclk);  in ci_trim_dpm_states()
3732 				  state->performance_levels[0].mclk,  in ci_trim_dpm_states()
3733 				  state->performance_levels[high_limit_count].mclk);  in ci_trim_dpm_states()
3736 				state->performance_levels[0].pcie_gen,  in ci_trim_dpm_states()
3737 				state->performance_levels[0].pcie_lane,  in ci_trim_dpm_states()
3738 				state->performance_levels[high_limit_count].pcie_gen,  in ci_trim_dpm_states()
3739 				state->performance_levels[high_limit_count].pcie_lane);  in ci_trim_dpm_states()
3822 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3824 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3863 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
3864 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4766 		pcie_speed = state->performance_levels[i].pcie_gen;  in ci_get_maximum_link_speed()
5441 	struct ci_pl *pl = &ps->performance_levels[index];  in ci_parse_pplib_clock_info()
5927 		pl = &ps->performance_levels[i];  in ci_dpm_print_power_state()
5954 		return requested_state->performance_levels[0].sclk;  in ci_dpm_get_sclk()
5956 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()
5965 		return requested_state->performance_levels[0].mclk;  in ci_dpm_get_mclk()
5967 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ci_dpm_get_mclk()