410 	SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;  in ci_populate_bapm_parameters_in_dpm_table()  local
418 	dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
419 	dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
421 	dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;  in ci_populate_bapm_parameters_in_dpm_table()
422 	dpm_table->GpuTjMax =  in ci_populate_bapm_parameters_in_dpm_table()
424 	dpm_table->GpuTjHyst = 8;  in ci_populate_bapm_parameters_in_dpm_table()
426 	dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;  in ci_populate_bapm_parameters_in_dpm_table()
429 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);  in ci_populate_bapm_parameters_in_dpm_table()
430 		dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);  in ci_populate_bapm_parameters_in_dpm_table()
432 		dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
433 		dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);  in ci_populate_bapm_parameters_in_dpm_table()
436 	dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);  in ci_populate_bapm_parameters_in_dpm_table()
443 				dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);  in ci_populate_bapm_parameters_in_dpm_table()
444 				dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);  in ci_populate_bapm_parameters_in_dpm_table()
2516 	for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {  in ci_do_program_memory_timing_parameters()
2517 		for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {  in ci_do_program_memory_timing_parameters()
2519 								   pi->dpm_table.sclk_table.dpm_levels[i].value,  in ci_do_program_memory_timing_parameters()
2520 								   pi->dpm_table.mclk_table.dpm_levels[j].value,  in ci_do_program_memory_timing_parameters()
2571 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)  in ci_get_dpm_level_enable_mask_value()  argument
2576 	for (i = dpm_table->count; i > 0; i--) {  in ci_get_dpm_level_enable_mask_value()
2578 		if (dpm_table->dpm_levels[i-1].enabled)  in ci_get_dpm_level_enable_mask_value()
2591 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_smc_link_level()  local
2594 	for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {  in ci_populate_smc_link_level()
2596 			(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;  in ci_populate_smc_link_level()
2598 			r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);  in ci_populate_smc_link_level()
2604 	pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;  in ci_populate_smc_link_level()
2606 		ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);  in ci_populate_smc_link_level()
3240 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_graphic_levels()  local
3250 	for (i = 0; i < dpm_table->sclk_table.count; i++) {  in ci_populate_all_graphic_levels()
3252 						       dpm_table->sclk_table.dpm_levels[i].value,  in ci_populate_all_graphic_levels()
3259 		if (i == (dpm_table->sclk_table.count - 1))  in ci_populate_all_graphic_levels()
3265 	pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;  in ci_populate_all_graphic_levels()
3267 		ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);  in ci_populate_all_graphic_levels()
3287 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_all_memory_levels()  local
3297 	for (i = 0; i < dpm_table->mclk_table.count; i++) {  in ci_populate_all_memory_levels()
3298 		if (dpm_table->mclk_table.dpm_levels[i].value == 0)  in ci_populate_all_memory_levels()
3301 						      dpm_table->mclk_table.dpm_levels[i].value,  in ci_populate_all_memory_levels()
3309 	if ((dpm_table->mclk_table.count >= 2) &&  in ci_populate_all_memory_levels()
3319 	pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;  in ci_populate_all_memory_levels()
3321 		ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);  in ci_populate_all_memory_levels()
3323 	pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =  in ci_populate_all_memory_levels()
3336 				      struct ci_single_dpm_table* dpm_table,  in ci_reset_single_dpm_table()  argument
3341 	dpm_table->count = count;  in ci_reset_single_dpm_table()
3343 		dpm_table->dpm_levels[i].enabled = false;  in ci_reset_single_dpm_table()
3346 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,  in ci_setup_pcie_table_entry()  argument
3349 	dpm_table->dpm_levels[index].value = pcie_gen;  in ci_setup_pcie_table_entry()
3350 	dpm_table->dpm_levels[index].param1 = pcie_lanes;  in ci_setup_pcie_table_entry()
3351 	dpm_table->dpm_levels[index].enabled = true;  in ci_setup_pcie_table_entry()
3370 				  &pi->dpm_table.pcie_speed_table,  in ci_setup_default_pcie_tables()
3374 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3378 		ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,  in ci_setup_default_pcie_tables()
3381 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,  in ci_setup_default_pcie_tables()
3384 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,  in ci_setup_default_pcie_tables()
3387 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,  in ci_setup_default_pcie_tables()
3390 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,  in ci_setup_default_pcie_tables()
3393 	ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,  in ci_setup_default_pcie_tables()
3397 	pi->dpm_table.pcie_speed_table.count = 6;  in ci_setup_default_pcie_tables()
3422 	memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));  in ci_setup_default_dpm_tables()
3425 				  &pi->dpm_table.sclk_table,  in ci_setup_default_dpm_tables()
3428 				  &pi->dpm_table.mclk_table,  in ci_setup_default_dpm_tables()
3431 				  &pi->dpm_table.vddc_table,  in ci_setup_default_dpm_tables()
3434 				  &pi->dpm_table.vddci_table,  in ci_setup_default_dpm_tables()
3437 				  &pi->dpm_table.mvdd_table,  in ci_setup_default_dpm_tables()
3440 	pi->dpm_table.sclk_table.count = 0;  in ci_setup_default_dpm_tables()
3443 		    (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3445 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =  in ci_setup_default_dpm_tables()
3447 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3449 			pi->dpm_table.sclk_table.count++;  in ci_setup_default_dpm_tables()
3453 	pi->dpm_table.mclk_table.count = 0;  in ci_setup_default_dpm_tables()
3456 		    (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3458 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =  in ci_setup_default_dpm_tables()
3460 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3462 			pi->dpm_table.mclk_table.count++;  in ci_setup_default_dpm_tables()
3467 		pi->dpm_table.vddc_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3469 		pi->dpm_table.vddc_table.dpm_levels[i].param1 =  in ci_setup_default_dpm_tables()
3471 		pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3473 	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;  in ci_setup_default_dpm_tables()
3478 			pi->dpm_table.vddci_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3480 			pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3482 		pi->dpm_table.vddci_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3488 			pi->dpm_table.mvdd_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3490 			pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3492 		pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;  in ci_setup_default_dpm_tables()
3590 	ret = ci_find_boot_level(&pi->dpm_table.sclk_table,  in ci_init_smc_table()
3594 	ret = ci_find_boot_level(&pi->dpm_table.mclk_table,  in ci_init_smc_table()
3627 	table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;  in ci_init_smc_table()
3665 				      struct ci_single_dpm_table *dpm_table,  in ci_trim_single_dpm_states()  argument
3670 	for (i = 0; i < dpm_table->count; i++) {  in ci_trim_single_dpm_states()
3671 		if ((dpm_table->dpm_levels[i].value < low_limit) ||  in ci_trim_single_dpm_states()
3672 		    (dpm_table->dpm_levels[i].value > high_limit))  in ci_trim_single_dpm_states()
3673 			dpm_table->dpm_levels[i].enabled = false;  in ci_trim_single_dpm_states()
3675 			dpm_table->dpm_levels[i].enabled = true;  in ci_trim_single_dpm_states()
3684 	struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;  in ci_trim_pcie_dpm_states()
3726 				  &pi->dpm_table.sclk_table,  in ci_trim_dpm_states()
3731 				  &pi->dpm_table.mclk_table,  in ci_trim_dpm_states()
3821 	struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
3823 	struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;  in ci_find_dpm_states_clocks_in_dpm_table()
3865 	struct ci_dpm_table *dpm_table = &pi->dpm_table;  in ci_populate_and_upload_sclk_mclk_dpm_levels()  local
3872 		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
3875 		dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4140 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);  in ci_generate_dpm_level_enable_mask()
4142 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);  in ci_generate_dpm_level_enable_mask()
4150 		ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);  in ci_generate_dpm_level_enable_mask()
4705 	for (i = 0; i < pi->dpm_table.mclk_table.count; i++)  in ci_convert_mc_reg_table_to_smc()
4707 						     pi->dpm_table.mclk_table.dpm_levels[i].value,  in ci_convert_mc_reg_table_to_smc()
4746 				    pi->dpm_table.mclk_table.count,  in ci_update_and_upload_mc_reg_table()
5638 	SMU7_Discrete_DpmTable  *dpm_table;  in ci_dpm_init()  local
5787 	dpm_table = &pi->smc_state_table;  in ci_dpm_init()
5791 		dpm_table->VRHotGpio = gpio.shift;  in ci_dpm_init()
5794 		dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()
5800 		dpm_table->AcDcGpio = gpio.shift;  in ci_dpm_init()
5803 		dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;  in ci_dpm_init()