3405 	struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =  in ci_setup_default_dpm_tables()  local
3413 	if (allowed_sclk_vddc_table == NULL)  in ci_setup_default_dpm_tables()
3415 	if (allowed_sclk_vddc_table->count < 1)  in ci_setup_default_dpm_tables()
3441 	for (i = 0; i < allowed_sclk_vddc_table->count; i++) {  in ci_setup_default_dpm_tables()
3444 		     allowed_sclk_vddc_table->entries[i].clk)) {  in ci_setup_default_dpm_tables()
3446 				allowed_sclk_vddc_table->entries[i].clk;  in ci_setup_default_dpm_tables()
3466 	for (i = 0; i < allowed_sclk_vddc_table->count; i++) {  in ci_setup_default_dpm_tables()
3468 			allowed_sclk_vddc_table->entries[i].v;  in ci_setup_default_dpm_tables()
3473 	pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;  in ci_setup_default_dpm_tables()
4881 	struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =  in ci_set_private_data_variables_based_on_pptable()  local
4888 	if (allowed_sclk_vddc_table == NULL)  in ci_set_private_data_variables_based_on_pptable()
4890 	if (allowed_sclk_vddc_table->count < 1)  in ci_set_private_data_variables_based_on_pptable()
4901 	pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;  in ci_set_private_data_variables_based_on_pptable()
4903 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;  in ci_set_private_data_variables_based_on_pptable()
4910 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;  in ci_set_private_data_variables_based_on_pptable()
4912 		allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;  in ci_set_private_data_variables_based_on_pptable()
4914 		allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;  in ci_set_private_data_variables_based_on_pptable()