49 #define DSS_CONTROL			DSS_REG(0x0040)  macro
367 	DUMPREG(dss, DSS_CONTROL);  in dss_dump_regs()
431 	REG_FLD_MOD(dss, DSS_CONTROL, b,		/* DISPC_CLK_SWITCH */  in dss_select_dispc_clk_source()
461 	REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos);	/* DSIx_CLK_SWITCH */  in dss_select_dsi_clk_source()
481 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_dra7()
489 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_dra7()
513 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap5()
520 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap5()
542 		REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap4()
549 	REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);  in dss_lcd_clk_mux_omap4()
709 	REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);  in dss_set_venc_output()
715 	REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);  in dss_set_dac_pwrdn_bgz()
733 		REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);  in dss_select_hdmi_venc_clk_source()
761 	REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);  in dss_dpi_select_source_omap4()
788 	REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);  in dss_dpi_select_source_omap5()
1396 	REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);  in dss_probe_hardware()
1401 	REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4);	/* venc dac demen */  in dss_probe_hardware()
1402 	REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3);	/* venc clock 4x enable */  in dss_probe_hardware()
1403 	REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2);	/* venc clock mode = normal */  in dss_probe_hardware()