121 		BUG();  in DISPC_DEFAULT_COLOR()
138 		BUG();  in DISPC_TRANS_COLOR()
149 		BUG();  in DISPC_TIMING_H()
156 		BUG();  in DISPC_TIMING_H()
167 		BUG();  in DISPC_TIMING_V()
174 		BUG();  in DISPC_TIMING_V()
185 		BUG();  in DISPC_POL_FREQ()
192 		BUG();  in DISPC_POL_FREQ()
203 		BUG();  in DISPC_DIVISORo()
210 		BUG();  in DISPC_DIVISORo()
228 		BUG();  in DISPC_SIZE_MGR()
239 		BUG();  in DISPC_DATA_CYCLE1()
246 		BUG();  in DISPC_DATA_CYCLE1()
257 		BUG();  in DISPC_DATA_CYCLE2()
264 		BUG();  in DISPC_DATA_CYCLE2()
275 		BUG();  in DISPC_DATA_CYCLE3()
282 		BUG();  in DISPC_DATA_CYCLE3()
293 		BUG();  in DISPC_CPR_COEF_R()
300 		BUG();  in DISPC_CPR_COEF_R()
311 		BUG();  in DISPC_CPR_COEF_G()
318 		BUG();  in DISPC_CPR_COEF_G()
329 		BUG();  in DISPC_CPR_COEF_B()
336 		BUG();  in DISPC_CPR_COEF_B()
356 		BUG();  in DISPC_OVL_BASE()
373 		BUG();  in DISPC_BA0_OFFSET()
389 		BUG();  in DISPC_BA1_OFFSET()
398 		BUG();  in DISPC_BA0_UV_OFFSET()
409 		BUG();  in DISPC_BA0_UV_OFFSET()
418 		BUG();  in DISPC_BA1_UV_OFFSET()
429 		BUG();  in DISPC_BA1_UV_OFFSET()
444 		BUG();  in DISPC_POS_OFFSET()
460 		BUG();  in DISPC_SIZE_OFFSET()
477 		BUG();  in DISPC_ATTR_OFFSET()
486 		BUG();  in DISPC_ATTR2_OFFSET()
497 		BUG();  in DISPC_ATTR2_OFFSET()
514 		BUG();  in DISPC_FIFO_THRESH_OFFSET()
531 		BUG();  in DISPC_FIFO_SIZE_STATUS_OFFSET()
548 		BUG();  in DISPC_ROW_INC_OFFSET()
565 		BUG();  in DISPC_PIX_INC_OFFSET()
578 		BUG();  in DISPC_WINDOW_SKIP_OFFSET()
581 		BUG();  in DISPC_WINDOW_SKIP_OFFSET()
594 		BUG();  in DISPC_TABLE_BA_OFFSET()
597 		BUG();  in DISPC_TABLE_BA_OFFSET()
606 		BUG();  in DISPC_FIR_OFFSET()
615 		BUG();  in DISPC_FIR_OFFSET()
624 		BUG();  in DISPC_FIR2_OFFSET()
635 		BUG();  in DISPC_FIR2_OFFSET()
644 		BUG();  in DISPC_PIC_SIZE_OFFSET()
653 		BUG();  in DISPC_PIC_SIZE_OFFSET()
663 		BUG();  in DISPC_ACCU0_OFFSET()
672 		BUG();  in DISPC_ACCU0_OFFSET()
681 		BUG();  in DISPC_ACCU2_0_OFFSET()
692 		BUG();  in DISPC_ACCU2_0_OFFSET()
701 		BUG();  in DISPC_ACCU1_OFFSET()
710 		BUG();  in DISPC_ACCU1_OFFSET()
719 		BUG();  in DISPC_ACCU2_1_OFFSET()
730 		BUG();  in DISPC_ACCU2_1_OFFSET()
740 		BUG();  in DISPC_FIR_COEF_H_OFFSET()
749 		BUG();  in DISPC_FIR_COEF_H_OFFSET()
759 		BUG();  in DISPC_FIR_COEF_H2_OFFSET()
770 		BUG();  in DISPC_FIR_COEF_H2_OFFSET()
780 		BUG();  in DISPC_FIR_COEF_HV_OFFSET()
789 		BUG();  in DISPC_FIR_COEF_HV_OFFSET()
799 		BUG();  in DISPC_FIR_COEF_HV2_OFFSET()
810 		BUG();  in DISPC_FIR_COEF_HV2_OFFSET()
820 		BUG();  in DISPC_CONV_COEF_OFFSET()
828 		BUG();  in DISPC_CONV_COEF_OFFSET()
838 		BUG();  in DISPC_FIR_COEF_V_OFFSET()
848 		BUG();  in DISPC_FIR_COEF_V_OFFSET()
858 		BUG();  in DISPC_FIR_COEF_V2_OFFSET()
869 		BUG();  in DISPC_FIR_COEF_V2_OFFSET()
886 		BUG();  in DISPC_PRELOAD_OFFSET()
905 		BUG();  in DISPC_MFLAG_THRESHOLD_OFFSET()