Lines Matching refs:subdev
26 wpr_header_dump(struct nvkm_subdev *subdev, const struct wpr_header *hdr) in wpr_header_dump() argument
28 nvkm_debug(subdev, "wprHeader\n"); in wpr_header_dump()
29 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); in wpr_header_dump()
30 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); in wpr_header_dump()
31 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); in wpr_header_dump()
32 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); in wpr_header_dump()
33 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); in wpr_header_dump()
37 wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr) in wpr_header_v1_dump() argument
39 nvkm_debug(subdev, "wprHeader\n"); in wpr_header_v1_dump()
40 nvkm_debug(subdev, "\tfalconID : %d\n", hdr->falcon_id); in wpr_header_v1_dump()
41 nvkm_debug(subdev, "\tlsbOffset : 0x%x\n", hdr->lsb_offset); in wpr_header_v1_dump()
42 nvkm_debug(subdev, "\tbootstrapOwner: %d\n", hdr->bootstrap_owner); in wpr_header_v1_dump()
43 nvkm_debug(subdev, "\tlazyBootstrap : %d\n", hdr->lazy_bootstrap); in wpr_header_v1_dump()
44 nvkm_debug(subdev, "\tbinVersion : %d\n", hdr->bin_version); in wpr_header_v1_dump()
45 nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); in wpr_header_v1_dump()
49 lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr) in lsb_header_tail_dump() argument
51 nvkm_debug(subdev, "lsbHeader\n"); in lsb_header_tail_dump()
52 nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off); in lsb_header_tail_dump()
53 nvkm_debug(subdev, "\tucodeSize : 0x%x\n", hdr->ucode_size); in lsb_header_tail_dump()
54 nvkm_debug(subdev, "\tdataSize : 0x%x\n", hdr->data_size); in lsb_header_tail_dump()
55 nvkm_debug(subdev, "\tblCodeSize : 0x%x\n", hdr->bl_code_size); in lsb_header_tail_dump()
56 nvkm_debug(subdev, "\tblImemOff : 0x%x\n", hdr->bl_imem_off); in lsb_header_tail_dump()
57 nvkm_debug(subdev, "\tblDataOff : 0x%x\n", hdr->bl_data_off); in lsb_header_tail_dump()
58 nvkm_debug(subdev, "\tblDataSize : 0x%x\n", hdr->bl_data_size); in lsb_header_tail_dump()
59 nvkm_debug(subdev, "\tappCodeOff : 0x%x\n", hdr->app_code_off); in lsb_header_tail_dump()
60 nvkm_debug(subdev, "\tappCodeSize : 0x%x\n", hdr->app_code_size); in lsb_header_tail_dump()
61 nvkm_debug(subdev, "\tappDataOff : 0x%x\n", hdr->app_data_off); in lsb_header_tail_dump()
62 nvkm_debug(subdev, "\tappDataSize : 0x%x\n", hdr->app_data_size); in lsb_header_tail_dump()
63 nvkm_debug(subdev, "\tflags : 0x%x\n", hdr->flags); in lsb_header_tail_dump()
67 lsb_header_dump(struct nvkm_subdev *subdev, struct lsb_header *hdr) in lsb_header_dump() argument
69 lsb_header_tail_dump(subdev, &hdr->tail); in lsb_header_dump()
73 lsb_header_v1_dump(struct nvkm_subdev *subdev, struct lsb_header_v1 *hdr) in lsb_header_v1_dump() argument
75 lsb_header_tail_dump(subdev, &hdr->tail); in lsb_header_v1_dump()
79 flcn_acr_desc_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc *hdr) in flcn_acr_desc_dump() argument
83 nvkm_debug(subdev, "acrDesc\n"); in flcn_acr_desc_dump()
84 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); in flcn_acr_desc_dump()
85 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); in flcn_acr_desc_dump()
86 nvkm_debug(subdev, "\tmmuMemRange : 0x%x\n", in flcn_acr_desc_dump()
88 nvkm_debug(subdev, "\tnoRegions : %d\n", in flcn_acr_desc_dump()
92 nvkm_debug(subdev, "\tregion[%d] :\n", i); in flcn_acr_desc_dump()
93 nvkm_debug(subdev, "\t startAddr : 0x%x\n", in flcn_acr_desc_dump()
95 nvkm_debug(subdev, "\t endAddr : 0x%x\n", in flcn_acr_desc_dump()
97 nvkm_debug(subdev, "\t regionId : %d\n", in flcn_acr_desc_dump()
99 nvkm_debug(subdev, "\t readMask : 0x%x\n", in flcn_acr_desc_dump()
101 nvkm_debug(subdev, "\t writeMask : 0x%x\n", in flcn_acr_desc_dump()
103 nvkm_debug(subdev, "\t clientMask : 0x%x\n", in flcn_acr_desc_dump()
107 nvkm_debug(subdev, "\tucodeBlobSize: %d\n", in flcn_acr_desc_dump()
109 nvkm_debug(subdev, "\tucodeBlobBase: 0x%llx\n", in flcn_acr_desc_dump()
111 nvkm_debug(subdev, "\tvprEnabled : %d\n", in flcn_acr_desc_dump()
113 nvkm_debug(subdev, "\tvprStart : 0x%x\n", in flcn_acr_desc_dump()
115 nvkm_debug(subdev, "\tvprEnd : 0x%x\n", in flcn_acr_desc_dump()
117 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n", in flcn_acr_desc_dump()
122 flcn_acr_desc_v1_dump(struct nvkm_subdev *subdev, struct flcn_acr_desc_v1 *hdr) in flcn_acr_desc_v1_dump() argument
126 nvkm_debug(subdev, "acrDesc\n"); in flcn_acr_desc_v1_dump()
127 nvkm_debug(subdev, "\twprRegionId : %d\n", hdr->wpr_region_id); in flcn_acr_desc_v1_dump()
128 nvkm_debug(subdev, "\twprOffset : 0x%x\n", hdr->wpr_offset); in flcn_acr_desc_v1_dump()
129 nvkm_debug(subdev, "\tmmuMemoryRange : 0x%x\n", in flcn_acr_desc_v1_dump()
131 nvkm_debug(subdev, "\tnoRegions : %d\n", in flcn_acr_desc_v1_dump()
135 nvkm_debug(subdev, "\tregion[%d] :\n", i); in flcn_acr_desc_v1_dump()
136 nvkm_debug(subdev, "\t startAddr : 0x%x\n", in flcn_acr_desc_v1_dump()
138 nvkm_debug(subdev, "\t endAddr : 0x%x\n", in flcn_acr_desc_v1_dump()
140 nvkm_debug(subdev, "\t regionId : %d\n", in flcn_acr_desc_v1_dump()
142 nvkm_debug(subdev, "\t readMask : 0x%x\n", in flcn_acr_desc_v1_dump()
144 nvkm_debug(subdev, "\t writeMask : 0x%x\n", in flcn_acr_desc_v1_dump()
146 nvkm_debug(subdev, "\t clientMask : 0x%x\n", in flcn_acr_desc_v1_dump()
148 nvkm_debug(subdev, "\t shadowMemStartAddr: 0x%x\n", in flcn_acr_desc_v1_dump()
152 nvkm_debug(subdev, "\tucodeBlobSize : %d\n", in flcn_acr_desc_v1_dump()
154 nvkm_debug(subdev, "\tucodeBlobBase : 0x%llx\n", in flcn_acr_desc_v1_dump()
156 nvkm_debug(subdev, "\tvprEnabled : %d\n", in flcn_acr_desc_v1_dump()
158 nvkm_debug(subdev, "\tvprStart : 0x%x\n", in flcn_acr_desc_v1_dump()
160 nvkm_debug(subdev, "\tvprEnd : 0x%x\n", in flcn_acr_desc_v1_dump()
162 nvkm_debug(subdev, "\thdcpPolicies : 0x%x\n", in flcn_acr_desc_v1_dump()