39 	if (nvkm_rd32(device, 0x400144) & 0x00010000)  in nv20_gr_chan_fini()
40 		chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;  in nv20_gr_chan_fini()
45 			if (!nvkm_rd32(device, 0x400700))  in nv20_gr_chan_fini()
186 	u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);  in nv20_gr_intr()
187 	u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);  in nv20_gr_intr()
188 	u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);  in nv20_gr_intr()
189 	u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);  in nv20_gr_intr()
193 	u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);  in nv20_gr_intr()
194 	u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;  in nv20_gr_intr()
244 			if (!nvkm_rd32(device, 0x400700))  in nv20_gr_init()
252 			if (!nvkm_rd32(device, 0x400700))  in nv20_gr_init()
287 	nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));  in nv20_gr_init()
289 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));  in nv20_gr_init()
294 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;  in nv20_gr_init()
296 	tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;  in nv20_gr_init()
301 	nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));  in nv20_gr_init()
302 	nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));  in nv20_gr_init()
304 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));  in nv20_gr_init()
306 	nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));  in nv20_gr_init()