420 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);  in nv50_outp_atomic_check()  local
429 		asyh->or.bpc = connector->display_info.bpc;  in nv50_outp_atomic_check()
502 	struct nv50_head_atom *asyh =  in nv50_dac_atomic_enable()  local
521 	core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);  in nv50_dac_atomic_enable()
522 	asyh->or.depth = 0;  in nv50_dac_atomic_enable()
1028 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);  in nv50_msto_atomic_check()  local
1048 		asyh->or.bpc = connector->display_info.bpc;  in nv50_msto_atomic_check()
1049 		asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,  in nv50_msto_atomic_check()
1064 	slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);  in nv50_msto_atomic_check()
1068 	asyh->dp.tu = slots;  in nv50_msto_atomic_check()
1089 	struct nv50_head_atom *asyh =  in nv50_msto_atomic_enable()  local
1118 	mstm->outp->update(mstm->outp, head->base.index, asyh, proto,  in nv50_msto_atomic_enable()
1119 			   nv50_dp_bpc_to_depth(asyh->or.bpc));  in nv50_msto_atomic_enable()
1611 		struct nv50_head_atom *asyh, u8 proto, u8 depth)  in nv50_sor_update()  argument
1616 	if (!asyh) {  in nv50_sor_update()
1623 		asyh->or.depth = depth;  in nv50_sor_update()
1626 	core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);  in nv50_sor_update()
1679 	struct nv50_head_atom *asyh =  in nv50_sor_atomic_enable()  local
1681 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;  in nv50_sor_atomic_enable()
1757 			if (asyh->or.bpc == 8)  in nv50_sor_atomic_enable()
1764 		depth = nv50_dp_bpc_to_depth(asyh->or.bpc);  in nv50_sor_atomic_enable()
1786 	nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);  in nv50_sor_atomic_enable()
1934 	struct nv50_head_atom *asyh =  in nv50_pior_atomic_enable()  local
1949 	switch (asyh->or.bpc) {  in nv50_pior_atomic_enable()
1950 	case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;  in nv50_pior_atomic_enable()
1951 	case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;  in nv50_pior_atomic_enable()
1952 	case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;  in nv50_pior_atomic_enable()
1953 	default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;  in nv50_pior_atomic_enable()
1966 	core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);  in nv50_pior_atomic_enable()
2126 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2130 			  asyh->clr.mask, asyh->set.mask);  in nv50_disp_atomic_commit_tail()
2137 		if (asyh->clr.mask) {  in nv50_disp_atomic_commit_tail()
2138 			nv50_head_flush_clr(head, asyh, atom->flush_disable);  in nv50_disp_atomic_commit_tail()
2217 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2221 			  asyh->set.mask, asyh->clr.mask);  in nv50_disp_atomic_commit_tail()
2223 		if (asyh->set.mask) {  in nv50_disp_atomic_commit_tail()
2224 			nv50_head_flush_set(head, asyh);  in nv50_disp_atomic_commit_tail()
2268 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
2272 			  asyh->set.mask, asyh->clr.mask);  in nv50_disp_atomic_commit_tail()
2274 		if (asyh->set.mask) {  in nv50_disp_atomic_commit_tail()
2275 			nv50_head_flush_set_wndw(head, asyh);  in nv50_disp_atomic_commit_tail()
2504 	struct nv50_head_atom *asyh;  in nv50_disp_atomic_check()  local
2515 			asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_check()
2516 			core->func->head->static_wndw_map(head, asyh);  in nv50_disp_atomic_check()