Lines Matching refs:regp
67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance() local
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
73 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); in nv_crtc_set_digital_vibrance()
75 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); in nv_crtc_set_digital_vibrance()
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening() local
87 regp->ramdac_634 = level; in nv_crtc_set_image_sharpening()
88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); in nv_crtc_set_image_sharpening()
125 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; in nv_crtc_calc_state_ext() local
126 struct nvkm_pll_vals *pv = ®p->pllvals; in nv_crtc_calc_state_ext()
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga() local
308 regp->MiscOutReg = 0x23; in nv_crtc_mode_set_vga()
310 regp->MiscOutReg |= 0x40; in nv_crtc_mode_set_vga()
312 regp->MiscOutReg |= 0x80; in nv_crtc_mode_set_vga()
320 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ in nv_crtc_mode_set_vga()
322 regp->MiscOutReg = 0x63; /* -hsync +vsync */ in nv_crtc_mode_set_vga()
324 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ in nv_crtc_mode_set_vga()
326 regp->MiscOutReg = 0x23; /* +hsync +vsync */ in nv_crtc_mode_set_vga()
332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; in nv_crtc_mode_set_vga()
335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; in nv_crtc_mode_set_vga()
337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; in nv_crtc_mode_set_vga()
338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; in nv_crtc_mode_set_vga()
339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; in nv_crtc_mode_set_vga()
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; in nv_crtc_mode_set_vga()
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; in nv_crtc_mode_set_vga()
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; in nv_crtc_mode_set_vga()
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | in nv_crtc_mode_set_vga()
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; in nv_crtc_mode_set_vga()
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | in nv_crtc_mode_set_vga()
353 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; in nv_crtc_mode_set_vga()
354 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | in nv_crtc_mode_set_vga()
362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; in nv_crtc_mode_set_vga()
363 …regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL… in nv_crtc_mode_set_vga()
366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; in nv_crtc_mode_set_vga()
367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; in nv_crtc_mode_set_vga()
368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
372 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; in nv_crtc_mode_set_vga()
373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); in nv_crtc_mode_set_vga()
374 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; in nv_crtc_mode_set_vga()
376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; in nv_crtc_mode_set_vga()
377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; in nv_crtc_mode_set_vga()
378 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; in nv_crtc_mode_set_vga()
379 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; in nv_crtc_mode_set_vga()
380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; in nv_crtc_mode_set_vga()
381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; in nv_crtc_mode_set_vga()
388 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = in nv_crtc_mode_set_vga()
390 regp->CRTC[NV_CIO_CRE_42] = in nv_crtc_mode_set_vga()
392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? in nv_crtc_mode_set_vga()
394 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | in nv_crtc_mode_set_vga()
399 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | in nv_crtc_mode_set_vga()
403 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | in nv_crtc_mode_set_vga()
410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; in nv_crtc_mode_set_vga()
411 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); in nv_crtc_mode_set_vga()
413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ in nv_crtc_mode_set_vga()
418 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; in nv_crtc_mode_set_vga()
419 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; in nv_crtc_mode_set_vga()
420 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
421 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
422 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ in nv_crtc_mode_set_vga()
424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ in nv_crtc_mode_set_vga()
425 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; in nv_crtc_mode_set_vga()
426 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; in nv_crtc_mode_set_vga()
428 regp->Attribute[0] = 0x00; /* standard colormap translation */ in nv_crtc_mode_set_vga()
429 regp->Attribute[1] = 0x01; in nv_crtc_mode_set_vga()
430 regp->Attribute[2] = 0x02; in nv_crtc_mode_set_vga()
431 regp->Attribute[3] = 0x03; in nv_crtc_mode_set_vga()
432 regp->Attribute[4] = 0x04; in nv_crtc_mode_set_vga()
433 regp->Attribute[5] = 0x05; in nv_crtc_mode_set_vga()
434 regp->Attribute[6] = 0x06; in nv_crtc_mode_set_vga()
435 regp->Attribute[7] = 0x07; in nv_crtc_mode_set_vga()
436 regp->Attribute[8] = 0x08; in nv_crtc_mode_set_vga()
437 regp->Attribute[9] = 0x09; in nv_crtc_mode_set_vga()
438 regp->Attribute[10] = 0x0A; in nv_crtc_mode_set_vga()
439 regp->Attribute[11] = 0x0B; in nv_crtc_mode_set_vga()
440 regp->Attribute[12] = 0x0C; in nv_crtc_mode_set_vga()
441 regp->Attribute[13] = 0x0D; in nv_crtc_mode_set_vga()
442 regp->Attribute[14] = 0x0E; in nv_crtc_mode_set_vga()
443 regp->Attribute[15] = 0x0F; in nv_crtc_mode_set_vga()
444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ in nv_crtc_mode_set_vga()
446 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; in nv_crtc_mode_set_vga()
447 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ in nv_crtc_mode_set_vga()
448 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
449 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; in nv_crtc_mode_set_vga()
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs() local
494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); in nv_crtc_mode_set_regs()
496 regp->crtc_eng_ctrl = 0; in nv_crtc_mode_set_regs()
499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; in nv_crtc_mode_set_regs()
505 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; in nv_crtc_mode_set_regs()
510 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | in nv_crtc_mode_set_regs()
514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; in nv_crtc_mode_set_regs()
516 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; in nv_crtc_mode_set_regs()
519 regp->CRTC[NV_CIO_CRE_53] = 0; in nv_crtc_mode_set_regs()
520 regp->CRTC[NV_CIO_CRE_54] = 0; in nv_crtc_mode_set_regs()
524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; in nv_crtc_mode_set_regs()
526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; in nv_crtc_mode_set_regs()
528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; in nv_crtc_mode_set_regs()
532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; in nv_crtc_mode_set_regs()
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; in nv_crtc_mode_set_regs()
546 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV… in nv_crtc_mode_set_regs()
548 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; in nv_crtc_mode_set_regs()
552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; in nv_crtc_mode_set_regs()
555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; in nv_crtc_mode_set_regs()
557 regp->crtc_830 = mode->crtc_vdisplay - 3; in nv_crtc_mode_set_regs()
558 regp->crtc_834 = mode->crtc_vdisplay - 1; in nv_crtc_mode_set_regs()
562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); in nv_crtc_mode_set_regs()
565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); in nv_crtc_mode_set_regs()
568 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; in nv_crtc_mode_set_regs()
570 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; in nv_crtc_mode_set_regs()
574 regp->CRTC[NV_CIO_CRE_85] = 0xFF; in nv_crtc_mode_set_regs()
575 regp->CRTC[NV_CIO_CRE_86] = 0x1; in nv_crtc_mode_set_regs()
578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; in nv_crtc_mode_set_regs()
581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); in nv_crtc_mode_set_regs()
587 regp->nv10_cursync = (1 << 25); in nv_crtc_mode_set_regs()
589 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | in nv_crtc_mode_set_regs()
593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; in nv_crtc_mode_set_regs()
595 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; in nv_crtc_mode_set_regs()
597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ in nv_crtc_mode_set_regs()
598 regp->tv_setup = 0; in nv_crtc_mode_set_regs()
603 regp->ramdac_8c0 = 0x100; in nv_crtc_mode_set_regs()
604 regp->ramdac_a20 = 0x0; in nv_crtc_mode_set_regs()
605 regp->ramdac_a24 = 0xfffff; in nv_crtc_mode_set_regs()
606 regp->ramdac_a34 = 0x1; in nv_crtc_mode_set_regs()
831 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_crtc_do_mode_set_base() local
862 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; in nv04_crtc_do_mode_set_base()
863 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; in nv04_crtc_do_mode_set_base()
864 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; in nv04_crtc_do_mode_set_base()
866 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; in nv04_crtc_do_mode_set_base()
867 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); in nv04_crtc_do_mode_set_base()
869 regp->ramdac_gen_ctrl); in nv04_crtc_do_mode_set_base()
871 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; in nv04_crtc_do_mode_set_base()
872 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = in nv04_crtc_do_mode_set_base()
874 regp->CRTC[NV_CIO_CRE_42] = in nv04_crtc_do_mode_set_base()
876 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); in nv04_crtc_do_mode_set_base()
877 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); in nv04_crtc_do_mode_set_base()
878 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); in nv04_crtc_do_mode_set_base()
881 regp->fb_start = nv_crtc->fb.offset & ~3; in nv04_crtc_do_mode_set_base()
882 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); in nv04_crtc_do_mode_set_base()
883 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); in nv04_crtc_do_mode_set_base()
889 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; in nv04_crtc_do_mode_set_base()
890 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; in nv04_crtc_do_mode_set_base()
891 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); in nv04_crtc_do_mode_set_base()
892 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); in nv04_crtc_do_mode_set_base()
895 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; in nv04_crtc_do_mode_set_base()
896 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); in nv04_crtc_do_mode_set_base()