48 	int (*get_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
50 	int (*set_param)(struct msm_gpu *gpu, struct msm_file_private *ctx,
52 	int (*hw_init)(struct msm_gpu *gpu);
53 	int (*pm_suspend)(struct msm_gpu *gpu);
54 	int (*pm_resume)(struct msm_gpu *gpu);
55 	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
56 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
57 	irqreturn_t (*irq)(struct msm_gpu *irq);
58 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
59 	void (*recover)(struct msm_gpu *gpu);
60 	void (*destroy)(struct msm_gpu *gpu);
63 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
66 	void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
69 	u64 (*gpu_busy)(struct msm_gpu *gpu, unsigned long *out_sample_rate);
70 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
72 	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
74 	void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp,
77 		(struct msm_gpu *gpu, struct platform_device *pdev);
79 		(struct msm_gpu *gpu);
80 	uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
150 struct msm_gpu {  struct
280 static inline struct msm_gpu *dev_to_gpu(struct device *dev)  in dev_to_gpu()  argument
287 	return container_of(adreno_smmu, struct msm_gpu, adreno_smmu);  in dev_to_gpu()
298 static inline bool msm_gpu_active(struct msm_gpu *gpu)  in msm_gpu_active()
438 static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio,  in msm_gpu_convert_priority()
536 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)  in gpu_write()
541 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)  in gpu_read()
546 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)  in gpu_rmw()
551 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)  in gpu_read64()
575 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)  in gpu_write64()
582 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
583 int msm_gpu_pm_resume(struct msm_gpu *gpu);
585 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx,
602 				 struct msm_gpu *gpu, int sysprof);
617 void msm_devfreq_init(struct msm_gpu *gpu);
618 void msm_devfreq_cleanup(struct msm_gpu *gpu);
619 void msm_devfreq_resume(struct msm_gpu *gpu);
620 void msm_devfreq_suspend(struct msm_gpu *gpu);
621 void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor);
622 void msm_devfreq_active(struct msm_gpu *gpu);
623 void msm_devfreq_idle(struct msm_gpu *gpu);
625 int msm_gpu_hw_init(struct msm_gpu *gpu);
627 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
628 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
629 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
632 void msm_gpu_retire(struct msm_gpu *gpu);
633 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit);
636 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
640 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task);
642 void msm_gpu_cleanup(struct msm_gpu *gpu);
644 struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
654 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)  in msm_gpu_crashstate_get()
670 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)  in msm_gpu_crashstate_put()