126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN()
128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG0()
130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG1()
132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG2()
134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG3()
136 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_TEST_DATAPATH()
138 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_PIN_SWAP()
140 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL()
142 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL()
144 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL()
146 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL()
148 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_LPRX_CTRL()
150 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_TX_DCTRL()