96 enum mdp4_dma {  enum
454 static inline uint32_t __offset_DMA(enum mdp4_dma idx)  in __offset_DMA()
463 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }  in REG_MDP4_DMA()
465 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)…  in REG_MDP4_DMA_CONFIG()
494 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_SIZE()
508 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_BASE()
510 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA…  in REG_MDP4_DMA_SRC_STRIDE()
512 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i…  in REG_MDP4_DMA_DST_SIZE()
526 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DM…  in REG_MDP4_DMA_CURSOR_SIZE()
540 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DM…  in REG_MDP4_DMA_CURSOR_BASE()
542 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA…  in REG_MDP4_DMA_CURSOR_POS()
556 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __o…  in REG_MDP4_DMA_CURSOR_BLEND_CONFIG()
566 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __of…  in REG_MDP4_DMA_CURSOR_BLEND_PARAM()
568 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offse…  in REG_MDP4_DMA_BLEND_TRANS_LOW()
570 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offs…  in REG_MDP4_DMA_BLEND_TRANS_HIGH()
572 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_D…  in REG_MDP4_DMA_FETCH_CONFIG()
574 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }  in REG_MDP4_DMA_CSC()
577 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __o…  in REG_MDP4_DMA_CSC_MV()
579 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 +…  in REG_MDP4_DMA_CSC_MV_VAL()
581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 +…  in REG_MDP4_DMA_CSC_PRE_BV()
583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000035…  in REG_MDP4_DMA_CSC_PRE_BV_VAL()
585 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 …  in REG_MDP4_DMA_CSC_POST_BV()
587 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_BV_VAL()
589 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 +…  in REG_MDP4_DMA_CSC_PRE_LV()
591 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000036…  in REG_MDP4_DMA_CSC_PRE_LV_VAL()
593 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 …  in REG_MDP4_DMA_CSC_POST_LV()
595 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_LV_VAL()