Lines Matching refs:lm
12 #define CTL_LAYER(lm) \ argument
13 (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
14 #define CTL_LAYER_EXT(lm) \ argument
15 (0x40 + (((lm) - LM_0) * 0x004))
16 #define CTL_LAYER_EXT2(lm) \ argument
17 (0x70 + (((lm) - LM_0) * 0x004))
18 #define CTL_LAYER_EXT3(lm) \ argument
19 (0xA0 + (((lm) - LM_0) * 0x004))
70 enum dpu_lm lm) in _mixer_stages() argument
76 if (lm == mixer[i].id) { in _mixer_stages()
205 enum dpu_lm lm) in dpu_hw_ctl_update_pending_flush_mixer() argument
207 switch (lm) { in dpu_hw_ctl_update_pending_flush_mixer()
381 enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg) in dpu_hw_ctl_setup_blendstage() argument
390 stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm); in dpu_hw_ctl_setup_blendstage()
508 DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg); in dpu_hw_ctl_setup_blendstage()
509 DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext); in dpu_hw_ctl_setup_blendstage()
510 DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2); in dpu_hw_ctl_setup_blendstage()
511 DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3); in dpu_hw_ctl_setup_blendstage()