74 void mcde_display_irq(struct mcde *mcde)  in mcde_display_irq()  argument
80 	mispp = readl(mcde->regs + MCDE_MISPP);  in mcde_display_irq()
81 	misovl = readl(mcde->regs + MCDE_MISOVL);  in mcde_display_irq()
82 	mischnl = readl(mcde->regs + MCDE_MISCHNL);  in mcde_display_irq()
92 	if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) {  in mcde_display_irq()
101 		if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {  in mcde_display_irq()
102 			spin_lock(&mcde->flow_lock);  in mcde_display_irq()
103 			if (--mcde->flow_active == 0) {  in mcde_display_irq()
104 				dev_dbg(mcde->dev, "TE0 IRQ\n");  in mcde_display_irq()
106 				val = readl(mcde->regs + MCDE_CRA0);  in mcde_display_irq()
108 				writel(val, mcde->regs + MCDE_CRA0);  in mcde_display_irq()
110 			spin_unlock(&mcde->flow_lock);  in mcde_display_irq()
116 		dev_dbg(mcde->dev, "chnl A vblank IRQ\n");  in mcde_display_irq()
120 		dev_dbg(mcde->dev, "chnl B vblank IRQ\n");  in mcde_display_irq()
124 		dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n");  in mcde_display_irq()
126 		dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n");  in mcde_display_irq()
128 		dev_dbg(mcde->dev, "chnl C0 TE IRQ\n");  in mcde_display_irq()
130 		dev_dbg(mcde->dev, "chnl C1 TE IRQ\n");  in mcde_display_irq()
131 	writel(mispp, mcde->regs + MCDE_RISPP);  in mcde_display_irq()
134 		drm_crtc_handle_vblank(&mcde->pipe.crtc);  in mcde_display_irq()
137 		dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl);  in mcde_display_irq()
138 	writel(misovl, mcde->regs + MCDE_RISOVL);  in mcde_display_irq()
141 		dev_info(mcde->dev, "some stray channel error IRQ %08x\n",  in mcde_display_irq()
143 	writel(mischnl, mcde->regs + MCDE_RISCHNL);  in mcde_display_irq()
146 void mcde_display_disable_irqs(struct mcde *mcde)  in mcde_display_disable_irqs()  argument
149 	writel(0, mcde->regs + MCDE_IMSCPP);  in mcde_display_disable_irqs()
150 	writel(0, mcde->regs + MCDE_IMSCOVL);  in mcde_display_disable_irqs()
151 	writel(0, mcde->regs + MCDE_IMSCCHNL);  in mcde_display_disable_irqs()
154 	writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);  in mcde_display_disable_irqs()
155 	writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL);  in mcde_display_disable_irqs()
156 	writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL);  in mcde_display_disable_irqs()
196 static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src,  in mcde_configure_extsrc()  argument
324 		dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",  in mcde_configure_extsrc()
328 	writel(val, mcde->regs + conf);  in mcde_configure_extsrc()
333 	writel(val, mcde->regs + cr);  in mcde_configure_extsrc()
338 static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl,  in mcde_configure_overlay()  argument
408 	writel(val, mcde->regs + conf1);  in mcde_configure_overlay()
432 		dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",  in mcde_configure_overlay()
460 	dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n",  in mcde_configure_overlay()
463 	writel(val, mcde->regs + conf2);  in mcde_configure_overlay()
466 	writel(mcde->stride, mcde->regs + ljinc);  in mcde_configure_overlay()
468 	writel(0, mcde->regs + crop);  in mcde_configure_overlay()
480 	writel(val, mcde->regs + cr);  in mcde_configure_overlay()
487 	writel(val, mcde->regs + comp);  in mcde_configure_overlay()
490 static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch,  in mcde_configure_channel()  argument
533 	switch (mcde->flow_mode) {  in mcde_configure_channel()
571 		dev_err(mcde->dev, "unknown flow mode %d\n",  in mcde_configure_channel()
572 			mcde->flow_mode);  in mcde_configure_channel()
576 	writel(val, mcde->regs + sync);  in mcde_configure_channel()
581 	writel(val, mcde->regs + conf);  in mcde_configure_channel()
589 	writel(val, mcde->regs + stat);  in mcde_configure_channel()
590 	writel(0, mcde->regs + bgcol);  in mcde_configure_channel()
596 		       mcde->regs + mux);  in mcde_configure_channel()
600 		       mcde->regs + mux);  in mcde_configure_channel()
608 	if (mcde->dpi_output) {  in mcde_configure_channel()
612 		dev_info(mcde->dev, "stripwidth: %d\n", stripwidth);  in mcde_configure_channel()
621 			writel(val, mcde->regs + MCDE_SYNCHCONFA);  in mcde_configure_channel()
624 			writel(val, mcde->regs + MCDE_SYNCHCONFB);  in mcde_configure_channel()
630 static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo,  in mcde_configure_fifo()  argument
695 	writel(val, mcde->regs + ctrl);  in mcde_configure_fifo()
700 	writel(val, mcde->regs + cr0);  in mcde_configure_fifo()
702 	spin_lock(&mcde->fifo_crx1_lock);  in mcde_configure_fifo()
703 	val = readl(mcde->regs + cr1);  in mcde_configure_fifo()
708 	if (mcde->dpi_output) {  in mcde_configure_fifo()
709 		struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);  in mcde_configure_fifo()
714 			dev_info(mcde->dev, "panel does not specify bus format, assume RGB888\n");  in mcde_configure_fifo()
734 			dev_err(mcde->dev, "unknown bus format, assume RGB888\n");  in mcde_configure_fifo()
744 	writel(val, mcde->regs + cr1);  in mcde_configure_fifo()
745 	spin_unlock(&mcde->fifo_crx1_lock);  in mcde_configure_fifo()
748 static void mcde_configure_dsi_formatter(struct mcde *mcde,  in mcde_configure_dsi_formatter()  argument
790 		dev_err(mcde->dev, "tried to configure a non-DSI formatter as DSI\n");  in mcde_configure_dsi_formatter()
799 	if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)  in mcde_configure_dsi_formatter()
801 	switch (mcde->mdsi->format) {  in mcde_configure_dsi_formatter()
811 		dev_err(mcde->dev,  in mcde_configure_dsi_formatter()
821 		dev_err(mcde->dev, "unknown DSI format\n");  in mcde_configure_dsi_formatter()
824 	writel(val, mcde->regs + conf0);  in mcde_configure_dsi_formatter()
826 	writel(formatter_frame, mcde->regs + frame);  in mcde_configure_dsi_formatter()
827 	writel(pkt_size, mcde->regs + pkt);  in mcde_configure_dsi_formatter()
828 	writel(0, mcde->regs + sync);  in mcde_configure_dsi_formatter()
834 	writel(val, mcde->regs + cmdw);  in mcde_configure_dsi_formatter()
840 	writel(0, mcde->regs + delay0);  in mcde_configure_dsi_formatter()
841 	writel(0, mcde->regs + delay1);  in mcde_configure_dsi_formatter()
844 static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo)  in mcde_enable_fifo()  argument
857 		dev_err(mcde->dev, "cannot enable FIFO %c\n",  in mcde_enable_fifo()
862 	spin_lock(&mcde->flow_lock);  in mcde_enable_fifo()
863 	val = readl(mcde->regs + cr);  in mcde_enable_fifo()
865 	writel(val, mcde->regs + cr);  in mcde_enable_fifo()
866 	mcde->flow_active++;  in mcde_enable_fifo()
867 	spin_unlock(&mcde->flow_lock);  in mcde_enable_fifo()
870 static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo,  in mcde_disable_fifo()  argument
885 		dev_err(mcde->dev, "cannot disable FIFO %c\n",  in mcde_disable_fifo()
890 	spin_lock(&mcde->flow_lock);  in mcde_disable_fifo()
891 	val = readl(mcde->regs + cr);  in mcde_disable_fifo()
893 	writel(val, mcde->regs + cr);  in mcde_disable_fifo()
894 	mcde->flow_active = 0;  in mcde_disable_fifo()
895 	spin_unlock(&mcde->flow_lock);  in mcde_disable_fifo()
901 	while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {  in mcde_disable_fifo()
904 			dev_err(mcde->dev,  in mcde_disable_fifo()
915 static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo,  in mcde_drain_pipe()  argument
946 	val = readl(mcde->regs + ctrl);  in mcde_drain_pipe()
948 		dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n");  in mcde_drain_pipe()
950 		mcde_enable_fifo(mcde, fifo);  in mcde_drain_pipe()
952 		writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw);  in mcde_drain_pipe()
954 		mcde_disable_fifo(mcde, fifo, true);  in mcde_drain_pipe()
973 static void mcde_setup_dpi(struct mcde *mcde, const struct drm_display_mode *mode,  in mcde_setup_dpi()  argument
976 	struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);  in mcde_setup_dpi()
989 	dev_info(mcde->dev, "output on DPI LCD from channel A\n");  in mcde_setup_dpi()
991 	dev_info(mcde->dev, "HSW: %d, HFP: %d, HBP: %d, VSW: %d, VFP: %d, VBP: %d\n",  in mcde_setup_dpi()
1027 	writel(val, mcde->regs + MCDE_CONF0);  in mcde_setup_dpi()
1030 	writel(0, mcde->regs + MCDE_TVCRA);  in mcde_setup_dpi()
1035 	writel(val, mcde->regs + MCDE_TVBL1A);  in mcde_setup_dpi()
1037 	writel(val, mcde->regs + MCDE_TVBL2A);  in mcde_setup_dpi()
1043 	writel(val, mcde->regs + MCDE_TVDVOA);  in mcde_setup_dpi()
1046 	writel((hbp - 1), mcde->regs + MCDE_TVTIM1A);  in mcde_setup_dpi()
1051 	writel(val, mcde->regs + MCDE_TVLBALWA);  in mcde_setup_dpi()
1054 	writel(0, mcde->regs + MCDE_TVISLA);  in mcde_setup_dpi()
1055 	writel(0, mcde->regs + MCDE_TVBLUA);  in mcde_setup_dpi()
1067 	writel(val, mcde->regs + MCDE_LCDTIM1A);  in mcde_setup_dpi()
1070 static void mcde_setup_dsi(struct mcde *mcde, const struct drm_display_mode *mode,  in mcde_setup_dsi()  argument
1083 	dev_info(mcde->dev, "output in %s mode, format %dbpp\n",  in mcde_setup_dsi()
1084 		 (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ?  in mcde_setup_dsi()
1086 		 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format));  in mcde_setup_dsi()
1088 		mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8;  in mcde_setup_dsi()
1089 	dev_info(mcde->dev, "Overlay CPP: %d bytes, DSI formatter CPP %d bytes\n",  in mcde_setup_dsi()
1106 	writel(val, mcde->regs + MCDE_CONF0);  in mcde_setup_dsi()
1120 	if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {  in mcde_setup_dsi()
1128 	dev_dbg(mcde->dev, "FIFO watermark after flooring: %d bytes\n",  in mcde_setup_dsi()
1130 	dev_dbg(mcde->dev, "Packet divisor: %d bytes\n", pkt_div);  in mcde_setup_dsi()
1135 	if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO))  in mcde_setup_dsi()
1138 	dev_dbg(mcde->dev, "DSI packet size: %d * %d bytes per line\n",  in mcde_setup_dsi()
1140 	dev_dbg(mcde->dev, "Overlay frame size: %u bytes\n",  in mcde_setup_dsi()
1144 	dev_dbg(mcde->dev, "Formatter frame size: %u bytes\n", formatter_frame);  in mcde_setup_dsi()
1158 	struct mcde *mcde = to_mcde(drm);  in mcde_display_enable()  local
1170 	ret = regulator_enable(mcde->epod);  in mcde_display_enable()
1181 	mcde_display_disable_irqs(mcde);  in mcde_display_enable()
1182 	writel(0, mcde->regs + MCDE_IMSCERR);  in mcde_display_enable()
1183 	writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);  in mcde_display_enable()
1185 	if (mcde->dpi_output)  in mcde_display_enable()
1186 		mcde_setup_dpi(mcde, mode, &fifo_wtrmrk);  in mcde_display_enable()
1188 		mcde_setup_dsi(mcde, mode, cpp, &fifo_wtrmrk,  in mcde_display_enable()
1191 	mcde->stride = mode->hdisplay * cpp;  in mcde_display_enable()
1193 		 mcde->stride);  in mcde_display_enable()
1196 	mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0);  in mcde_display_enable()
1205 	mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format);  in mcde_display_enable()
1212 	mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0,  in mcde_display_enable()
1219 	mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode);  in mcde_display_enable()
1221 	if (mcde->dpi_output) {  in mcde_display_enable()
1225 		mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DPI_FORMATTER_0,  in mcde_display_enable()
1229 		lcd_freq = clk_round_rate(mcde->fifoa_clk, mode->clock * 1000);  in mcde_display_enable()
1230 		ret = clk_set_rate(mcde->fifoa_clk, lcd_freq);  in mcde_display_enable()
1232 			dev_err(mcde->dev, "failed to set LCD clock rate %lu Hz\n",  in mcde_display_enable()
1234 		ret = clk_prepare_enable(mcde->fifoa_clk);  in mcde_display_enable()
1236 			dev_err(mcde->dev, "failed to enable FIFO A DPI clock\n");  in mcde_display_enable()
1239 		dev_info(mcde->dev, "LCD FIFO A clk rate %lu Hz\n",  in mcde_display_enable()
1240 			 clk_get_rate(mcde->fifoa_clk));  in mcde_display_enable()
1243 		mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0,  in mcde_display_enable()
1250 		mcde_dsi_enable(mcde->bridge);  in mcde_display_enable()
1253 		mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0,  in mcde_display_enable()
1257 	switch (mcde->flow_mode) {  in mcde_display_enable()
1266 		writel(val, mcde->regs + MCDE_VSCRC0);  in mcde_display_enable()
1268 		val = readl(mcde->regs + MCDE_CRC);  in mcde_display_enable()
1270 		writel(val, mcde->regs + MCDE_CRC);  in mcde_display_enable()
1287 	if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) {  in mcde_display_enable()
1288 		mcde_enable_fifo(mcde, MCDE_FIFO_A);  in mcde_display_enable()
1289 		dev_dbg(mcde->dev, "started MCDE video FIFO flow\n");  in mcde_display_enable()
1293 	val = readl(mcde->regs + MCDE_CR);  in mcde_display_enable()
1295 	writel(val, mcde->regs + MCDE_CR);  in mcde_display_enable()
1304 	struct mcde *mcde = to_mcde(drm);  in mcde_display_disable()  local
1311 	mcde_disable_fifo(mcde, MCDE_FIFO_A, true);  in mcde_display_disable()
1313 	if (mcde->dpi_output) {  in mcde_display_disable()
1314 		clk_disable_unprepare(mcde->fifoa_clk);  in mcde_display_disable()
1317 		mcde_dsi_disable(mcde->bridge);  in mcde_display_disable()
1329 	ret = regulator_disable(mcde->epod);  in mcde_display_disable()
1338 static void mcde_start_flow(struct mcde *mcde)  in mcde_start_flow()  argument
1341 	if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW)  in mcde_start_flow()
1342 		mcde_dsi_te_request(mcde->mdsi);  in mcde_start_flow()
1345 	mcde_enable_fifo(mcde, MCDE_FIFO_A);  in mcde_start_flow()
1354 	if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {  in mcde_start_flow()
1357 		       mcde->regs + MCDE_CHNL0SYNCHSW);  in mcde_start_flow()
1366 		mcde_disable_fifo(mcde, MCDE_FIFO_A, true);  in mcde_start_flow()
1369 	dev_dbg(mcde->dev, "started MCDE FIFO flow\n");  in mcde_start_flow()
1372 static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address)  in mcde_set_extsrc()  argument
1375 	writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0);  in mcde_set_extsrc()
1380 	writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1);  in mcde_set_extsrc()
1388 	struct mcde *mcde = to_mcde(drm);  in mcde_display_update()  local
1411 			dev_dbg(mcde->dev, "arm vblank event\n");  in mcde_display_update()
1414 			dev_dbg(mcde->dev, "insert fake vblank event\n");  in mcde_display_update()
1427 		mcde_set_extsrc(mcde, drm_fb_dma_get_gem_addr(fb, pstate, 0));  in mcde_display_update()
1428 		dev_info_once(mcde->dev, "first update of display contents\n");  in mcde_display_update()
1433 		if (mcde->flow_active == 0)  in mcde_display_update()
1434 			mcde_start_flow(mcde);  in mcde_display_update()
1441 		dev_info(mcde->dev, "ignored a display update\n");  in mcde_display_update()
1449 	struct mcde *mcde = to_mcde(drm);  in mcde_display_enable_vblank()  local
1459 	writel(val, mcde->regs + MCDE_IMSCPP);  in mcde_display_enable_vblank()
1468 	struct mcde *mcde = to_mcde(drm);  in mcde_display_disable_vblank()  local
1471 	writel(0, mcde->regs + MCDE_IMSCPP);  in mcde_display_disable_vblank()
1473 	writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);  in mcde_display_disable_vblank()
1487 	struct mcde *mcde = to_mcde(drm);  in mcde_display_init()  local
1508 	ret = mcde_init_clock_divider(mcde);  in mcde_display_init()
1512 	ret = drm_simple_display_pipe_init(drm, &mcde->pipe,  in mcde_display_init()
1516 					   mcde->connector);  in mcde_display_init()