Lines Matching refs:base_reg
80 void __iomem *base_reg; member
101 dcss_writel(val, dtg->base_reg + ofs); in dcss_dtg_write()
112 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS); in dcss_dtg_irq_handler()
119 dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_irq_handler()
134 dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_irq_config()
163 dtg->base_reg = ioremap(dtg_base, SZ_4K); in dcss_dtg_init()
164 if (!dtg->base_reg) { in dcss_dtg_init()
185 iounmap(dtg->base_reg); in dcss_dtg_init()
197 if (dtg->base_reg) in dcss_dtg_exit()
198 iounmap(dtg->base_reg); in dcss_dtg_exit()
330 dtg->base_reg + DCSS_DTG_TC_CONTROL_STATUS); in dcss_dtg_shutoff()
363 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS); in dcss_dtg_vblank_irq_enable()
365 dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_vblank_irq_enable()
368 dcss_update(mask, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_vblank_irq_enable()
377 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS); in dcss_dtg_ctxld_kick_irq_enable()
381 dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_ctxld_kick_irq_enable()
385 dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_ctxld_kick_irq_enable()
397 dcss_update(mask, LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK); in dcss_dtg_ctxld_kick_irq_enable()
402 dcss_update(LINE1_IRQ, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL); in dcss_dtg_vblank_irq_clear()
407 return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ); in dcss_dtg_vblank_irq_valid()