64 		void *p_data, unsigned int bytes, bool read)  in failsafe_emulate_mmio_rw()  argument
79 					bytes);  in failsafe_emulate_mmio_rw()
82 					bytes);  in failsafe_emulate_mmio_rw()
87 			memcpy(p_data, pt, bytes);  in failsafe_emulate_mmio_rw()
89 			memcpy(pt, p_data, bytes);  in failsafe_emulate_mmio_rw()
106 		void *p_data, unsigned int bytes)  in intel_vgpu_emulate_mmio_read()  argument
114 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
121 	if (drm_WARN_ON(&i915->drm, bytes > 8))  in intel_vgpu_emulate_mmio_read()
128 		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))  in intel_vgpu_emulate_mmio_read()
131 				!reg_is_gtt(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_read()
135 				p_data, bytes);  in intel_vgpu_emulate_mmio_read()
142 		ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_read()
146 	if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_read()
150 		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))  in intel_vgpu_emulate_mmio_read()
154 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);  in intel_vgpu_emulate_mmio_read()
164 			offset, bytes);  in intel_vgpu_emulate_mmio_read()
181 		void *p_data, unsigned int bytes)  in intel_vgpu_emulate_mmio_write()  argument
189 		failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
197 	if (drm_WARN_ON(&i915->drm, bytes > 8))  in intel_vgpu_emulate_mmio_write()
204 		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))  in intel_vgpu_emulate_mmio_write()
207 				!reg_is_gtt(gvt, offset + bytes - 1)))  in intel_vgpu_emulate_mmio_write()
211 				p_data, bytes);  in intel_vgpu_emulate_mmio_write()
218 		ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes);  in intel_vgpu_emulate_mmio_write()
222 	ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);  in intel_vgpu_emulate_mmio_write()
231 		     bytes);  in intel_vgpu_emulate_mmio_write()