131 			rps->pm_iir |= GEN6_PM_RP_UP_THRESHOLD;  in rps_timer()
136 			rps->pm_iir |= GEN6_PM_RP_DOWN_THRESHOLD;  in rps_timer()
226 	rps->pm_iir = 0;  in rps_reset_interrupts()
875 	rps->pm_iir = 0;  in intel_rps_unpark()
1751 static u32 vlv_wa_c0_ei(struct intel_rps *rps, u32 pm_iir)  in vlv_wa_c0_ei()  argument
1758 	if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)  in vlv_wa_c0_ei()
1798 	u32 pm_iir = 0;  in rps_work()  local
1801 	pm_iir = fetch_and_zero(&rps->pm_iir) & rps->pm_events;  in rps_work()
1806 	if (!pm_iir && !client_boost)  in rps_work()
1815 	pm_iir |= vlv_wa_c0_ei(rps, pm_iir);  in rps_work()
1826 		 pm_iir, str_yes_no(client_boost),  in rps_work()
1832 	} else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {  in rps_work()
1842 	} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {  in rps_work()
1848 	} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {  in rps_work()
1881 void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)  in gen11_rps_irq_handler()  argument
1884 	const u32 events = rps->pm_events & pm_iir;  in gen11_rps_irq_handler()
1895 	rps->pm_iir |= events;  in gen11_rps_irq_handler()
1899 void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)  in gen6_rps_irq_handler()  argument
1904 	events = pm_iir & rps->pm_events;  in gen6_rps_irq_handler()
1911 		rps->pm_iir |= events;  in gen6_rps_irq_handler()
1920 	if (pm_iir & PM_VEBOX_USER_INTERRUPT)  in gen6_rps_irq_handler()
1921 		intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10);  in gen6_rps_irq_handler()
1923 	if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)  in gen6_rps_irq_handler()
1924 		DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);  in gen6_rps_irq_handler()