355 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
377 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
400 			&crtc_state->wm.skl.optimal.planes[plane_id];  in tgl_crtc_can_enable_sagv()
479 		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;  in intel_compute_sagv_mask()
680 	crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;  in skl_crtc_allocate_ddb()
681 	crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;  in skl_crtc_allocate_ddb()
1473 	memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb));  in skl_crtc_allocate_plane_ddb()
1474 	memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));  in skl_crtc_allocate_plane_ddb()
1487 	skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],  in skl_crtc_allocate_plane_ddb()
1500 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1504 					&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1544 			&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1546 			&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_crtc_allocate_plane_ddb()
1548 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1575 				&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1577 				&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_crtc_allocate_plane_ddb()
1579 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1604 			&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1606 			&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_crtc_allocate_plane_ddb()
1608 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
2087 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];  in skl_build_plane_wm_single()
2115 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane->id];  in skl_build_plane_wm_uv()
2137 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in skl_build_plane_wm()
2167 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in icl_build_plane_wm()
2230 	crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;  in skl_build_pipe_wm()
2270 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_write_plane_wm()
2272 		&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_write_plane_wm()
2274 		&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_write_plane_wm()
2307 	const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_write_cursor_wm()
2309 		&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_write_cursor_wm()
2406 		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],  in skl_ddb_add_affected_planes()
2407 					&new_crtc_state->wm.skl.plane_ddb[plane_id]) &&  in skl_ddb_add_affected_planes()
2408 		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],  in skl_ddb_add_affected_planes()
2409 					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]))  in skl_ddb_add_affected_planes()
2571 		old_pipe_wm = &old_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
2572 		new_pipe_wm = &new_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
2578 			old = &old_crtc_state->wm.skl.plane_ddb[plane_id];  in skl_print_wm_changes()
2579 			new = &new_crtc_state->wm.skl.plane_ddb[plane_id];  in skl_print_wm_changes()
2765 						 &old_crtc_state->wm.skl.optimal,  in skl_wm_add_affected_planes()
2766 						 &new_crtc_state->wm.skl.optimal))  in skl_wm_add_affected_planes()
2896 		memset(&crtc_state->wm.skl.optimal, 0,  in skl_wm_get_hw_state()
2897 		       sizeof(crtc_state->wm.skl.optimal));  in skl_wm_get_hw_state()
2899 			skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);  in skl_wm_get_hw_state()
2900 		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;  in skl_wm_get_hw_state()
2906 				&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_wm_get_hw_state()
2908 				&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_wm_get_hw_state()
2929 		crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;  in skl_wm_get_hw_state()
2930 		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;  in skl_wm_get_hw_state()
2934 			skl_ddb_dbuf_slice_mask(i915, &crtc_state->wm.skl.ddb);  in skl_wm_get_hw_state()
2958 		entries[crtc->pipe] = crtc_state->wm.skl.ddb;  in skl_dbuf_is_misconfigured()
2971 		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries,  in skl_dbuf_is_misconfigured()
3011 		memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb));  in skl_wm_sanitize()
3024 	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;  in intel_wm_state_verify()
3121 		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];  in intel_wm_state_verify()