Lines Matching refs:dpll
310 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
322 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
324 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
327 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
339 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
351 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
370 const struct dpll *clock) in intel_pll_is_valid()
441 const struct dpll *match_clock, in i9xx_find_best_dpll()
442 struct dpll *best_clock) in i9xx_find_best_dpll()
445 struct dpll clock; in i9xx_find_best_dpll()
499 const struct dpll *match_clock, in pnv_find_best_dpll()
500 struct dpll *best_clock) in pnv_find_best_dpll()
503 struct dpll clock; in pnv_find_best_dpll()
555 const struct dpll *match_clock, in g4x_find_best_dpll()
556 struct dpll *best_clock) in g4x_find_best_dpll()
559 struct dpll clock; in g4x_find_best_dpll()
606 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
607 const struct dpll *best_clock, in vlv_PLL_is_optimal()
649 const struct dpll *match_clock, in vlv_find_best_dpll()
650 struct dpll *best_clock) in vlv_find_best_dpll()
654 struct dpll clock; in vlv_find_best_dpll()
707 const struct dpll *match_clock, in chv_find_best_dpll()
708 struct dpll *best_clock) in chv_find_best_dpll()
713 struct dpll clock; in chv_find_best_dpll()
763 struct dpll *best_clock) in bxt_find_best_dpll()
773 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
775 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
778 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) in pnv_dpll_compute_fp() argument
780 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
784 const struct dpll *clock, in i9xx_update_pll_dividers()
785 const struct dpll *reduced_clock) in i9xx_update_pll_dividers()
804 const struct dpll *clock, in i9xx_compute_dpll()
805 const struct dpll *reduced_clock) in i9xx_compute_dpll()
809 u32 dpll; in i9xx_compute_dpll() local
813 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
816 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
818 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
822 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
828 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
831 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
835 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
836 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
838 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
841 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
847 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
850 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
853 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
856 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
862 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
865 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
868 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
870 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
872 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
873 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
883 const struct dpll *clock, in i8xx_compute_dpll()
884 const struct dpll *reduced_clock) in i8xx_compute_dpll()
888 u32 dpll; in i8xx_compute_dpll() local
892 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
895 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
898 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
900 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
902 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
921 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
925 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
927 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
929 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
930 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
996 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
998 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1002 const struct dpll *clock, in ilk_update_pll_dividers()
1003 const struct dpll *reduced_clock) in ilk_update_pll_dividers()
1035 const struct dpll *clock, in ilk_compute_dpll()
1036 const struct dpll *reduced_clock) in ilk_compute_dpll()
1040 u32 dpll; in ilk_compute_dpll() local
1044 dpll = 0; in ilk_compute_dpll()
1047 dpll |= DPLLB_MODE_LVDS; in ilk_compute_dpll()
1049 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_compute_dpll()
1051 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1056 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1059 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1077 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1080 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1082 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1086 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
1089 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_compute_dpll()
1092 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_compute_dpll()
1095 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_compute_dpll()
1102 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_compute_dpll()
1104 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_compute_dpll()
1106 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
1108 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1150 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1153 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1154 &crtc_state->dpll); in ilk_crtc_compute_clock()
1160 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1183 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1186 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1190 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1201 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1204 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1208 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1224 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1233 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1249 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1259 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1298 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1301 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1302 &crtc_state->dpll); in g4x_crtc_compute_clock()
1304 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1336 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1339 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1340 &crtc_state->dpll); in pnv_crtc_compute_clock()
1342 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1372 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1375 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1376 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1378 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1412 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1415 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1416 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1418 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1478 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1502 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1505 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1519 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1521 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1523 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1525 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1527 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1529 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1531 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1533 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1535 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1550 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1568 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1569 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1584 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1589 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1635 bestn = crtc_state->dpll.n; in vlv_prepare_pll()
1636 bestm1 = crtc_state->dpll.m1; in vlv_prepare_pll()
1637 bestm2 = crtc_state->dpll.m2; in vlv_prepare_pll()
1638 bestp1 = crtc_state->dpll.p1; in vlv_prepare_pll()
1639 bestp2 = crtc_state->dpll.p2; in vlv_prepare_pll()
1720 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1741 crtc_state->dpll_hw_state.dpll & in vlv_enable_pll()
1744 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
1765 bestn = crtc_state->dpll.n; in chv_prepare_pll()
1766 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1767 bestm1 = crtc_state->dpll.m1; in chv_prepare_pll()
1768 bestm2 = crtc_state->dpll.m2 >> 22; in chv_prepare_pll()
1769 bestp1 = crtc_state->dpll.p1; in chv_prepare_pll()
1770 bestp2 = crtc_state->dpll.p2; in chv_prepare_pll()
1771 vco = crtc_state->dpll.vco; in chv_prepare_pll()
1873 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
1893 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
1895 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
1938 const struct dpll *dpll) in vlv_force_pll_on() argument
1949 crtc_state->dpll = *dpll; in vlv_force_pll_on()