2147 	const struct intel_cdclk_state *new_cdclk_state =  in intel_set_cdclk_pre_plane_update()  local
2149 	enum pipe pipe = new_cdclk_state->pipe;  in intel_set_cdclk_pre_plane_update()
2152 				 &new_cdclk_state->actual))  in intel_set_cdclk_pre_plane_update()
2156 	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {  in intel_set_cdclk_pre_plane_update()
2157 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);  in intel_set_cdclk_pre_plane_update()
2159 		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);  in intel_set_cdclk_pre_plane_update()
2176 	const struct intel_cdclk_state *new_cdclk_state =  in intel_set_cdclk_post_plane_update()  local
2178 	enum pipe pipe = new_cdclk_state->pipe;  in intel_set_cdclk_post_plane_update()
2181 				 &new_cdclk_state->actual))  in intel_set_cdclk_post_plane_update()
2185 	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {  in intel_set_cdclk_post_plane_update()
2186 		drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);  in intel_set_cdclk_post_plane_update()
2188 		intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);  in intel_set_cdclk_post_plane_update()
2657 	const struct intel_cdclk_state *new_cdclk_state;  in intel_cdclk_atomic_check()  local
2679 	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);  in intel_cdclk_atomic_check()
2681 	if (new_cdclk_state &&  in intel_cdclk_atomic_check()
2682 	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)  in intel_cdclk_atomic_check()
2706 	struct intel_cdclk_state *new_cdclk_state;  in intel_modeset_calc_cdclk()  local
2710 	new_cdclk_state = intel_atomic_get_cdclk_state(state);  in intel_modeset_calc_cdclk()
2711 	if (IS_ERR(new_cdclk_state))  in intel_modeset_calc_cdclk()
2712 		return PTR_ERR(new_cdclk_state);  in intel_modeset_calc_cdclk()
2716 	new_cdclk_state->active_pipes =  in intel_modeset_calc_cdclk()
2719 	ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);  in intel_modeset_calc_cdclk()
2724 				&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2729 		ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);  in intel_modeset_calc_cdclk()
2732 	} else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||  in intel_modeset_calc_cdclk()
2733 		   old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||  in intel_modeset_calc_cdclk()
2735 				       &new_cdclk_state->logical)) {  in intel_modeset_calc_cdclk()
2736 		ret = intel_atomic_lock_global_state(&new_cdclk_state->base);  in intel_modeset_calc_cdclk()
2743 	if (is_power_of_2(new_cdclk_state->active_pipes) &&  in intel_modeset_calc_cdclk()
2746 					&new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2750 		pipe = ilog2(new_cdclk_state->active_pipes);  in intel_modeset_calc_cdclk()
2763 				   &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2768 					 &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2772 		new_cdclk_state->pipe = pipe;  in intel_modeset_calc_cdclk()
2778 					     &new_cdclk_state->actual)) {  in intel_modeset_calc_cdclk()
2790 		    new_cdclk_state->logical.cdclk,  in intel_modeset_calc_cdclk()
2791 		    new_cdclk_state->actual.cdclk);  in intel_modeset_calc_cdclk()
2794 		    new_cdclk_state->logical.voltage_level,  in intel_modeset_calc_cdclk()
2795 		    new_cdclk_state->actual.voltage_level);  in intel_modeset_calc_cdclk()