Lines Matching refs:dpll
104 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
155 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
158 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
164 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
165 dpll |= in psb_intel_crtc_mode_set()
170 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
173 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
176 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
179 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in psb_intel_crtc_mode_set()
182 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in psb_intel_crtc_mode_set()
189 dpll |= 3; in psb_intel_crtc_mode_set()
191 dpll |= PLL_REF_INPUT_DREFCLK; in psb_intel_crtc_mode_set()
206 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()
215 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()
217 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
218 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
252 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
253 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
258 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
260 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
307 u32 dpll; in psb_intel_crtc_clock_get() local
314 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
315 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in psb_intel_crtc_clock_get()
322 dpll = p->dpll; in psb_intel_crtc_clock_get()
324 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in psb_intel_crtc_clock_get()
339 ffs((dpll & in psb_intel_crtc_clock_get()
344 if ((dpll & PLL_REF_INPUT_MASK) == in psb_intel_crtc_clock_get()
351 if (dpll & PLL_P1_DIVIDE_BY_TWO) in psb_intel_crtc_clock_get()
355 ((dpll & in psb_intel_crtc_clock_get()
359 if (dpll & PLL_P2_DIVIDE_BY_4) in psb_intel_crtc_clock_get()