Lines Matching refs:ast
42 struct ast_private *ast = to_ast_private(dev); in ast_enable_vga() local
44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
50 struct ast_private *ast = to_ast_private(dev); in ast_enable_mmio() local
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
58 struct ast_private *ast = to_ast_private(dev); in ast_is_vga_enabled() local
61 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT); in ast_is_vga_enabled()
73 struct ast_private *ast = to_ast_private(dev); in ast_set_def_ext_reg() local
80 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
82 if (ast->chip == AST2300 || ast->chip == AST2400 || in ast_set_def_ext_reg()
83 ast->chip == AST2500) { in ast_set_def_ext_reg()
93 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
103 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
107 if (ast->chip == AST2300 || ast->chip == AST2400 || in ast_set_def_ext_reg()
108 ast->chip == AST2500) in ast_set_def_ext_reg()
110 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
113 u32 ast_mindwm(struct ast_private *ast, u32 r) in ast_mindwm() argument
117 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_mindwm()
118 ast_write32(ast, 0xf000, 0x1); in ast_mindwm()
121 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_mindwm()
123 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); in ast_mindwm()
126 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v) in ast_moutdwm() argument
129 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_moutdwm()
130 ast_write32(ast, 0xf000, 0x1); in ast_moutdwm()
132 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_moutdwm()
134 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); in ast_moutdwm()
165 static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen) in mmctestburst2_ast2150() argument
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
170 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); in mmctestburst2_ast2150()
173 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
175 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
180 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); in mmctestburst2_ast2150()
183 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
185 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
189 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; in mmctestburst2_ast2150()
190 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
195 static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
199 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
200 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
203 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
205 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
209 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
210 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
215 static int cbrtest_ast2150(struct ast_private *ast) in cbrtest_ast2150() argument
220 if (mmctestburst2_ast2150(ast, i)) in cbrtest_ast2150()
225 static int cbrscan_ast2150(struct ast_private *ast, int busw) in cbrscan_ast2150() argument
230 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); in cbrscan_ast2150()
232 if (cbrtest_ast2150(ast)) in cbrscan_ast2150()
242 static void cbrdlli_ast2150(struct ast_private *ast, int busw) in cbrdlli_ast2150() argument
252 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
253 data = cbrscan_ast2150(ast, busw); in cbrdlli_ast2150()
269 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
276 struct ast_private *ast = to_ast_private(dev); in ast_init_dram_reg() local
281 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
284 if (ast->chip == AST2000) { in ast_init_dram_reg()
286 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
287 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
288 ast_write32(ast, 0x10100, 0xa8); in ast_init_dram_reg()
292 } while (ast_read32(ast, 0x10100) != 0xa8); in ast_init_dram_reg()
294 if (ast->chip == AST2100 || ast->chip == 2200) in ast_init_dram_reg()
299 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
300 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
301 ast_write32(ast, 0x12000, 0x1688A8A8); in ast_init_dram_reg()
304 } while (ast_read32(ast, 0x12000) != 0x01); in ast_init_dram_reg()
306 ast_write32(ast, 0x10000, 0xfc600309); in ast_init_dram_reg()
309 } while (ast_read32(ast, 0x10000) != 0x01); in ast_init_dram_reg()
316 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) { in ast_init_dram_reg()
318 if (ast->dram_type == AST_DRAM_1Gx16) in ast_init_dram_reg()
320 else if (ast->dram_type == AST_DRAM_1Gx32) in ast_init_dram_reg()
323 temp = ast_read32(ast, 0x12070); in ast_init_dram_reg()
326 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); in ast_init_dram_reg()
328 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); in ast_init_dram_reg()
333 data = ast_read32(ast, 0x10120); in ast_init_dram_reg()
335 data = ast_read32(ast, 0x10004); in ast_init_dram_reg()
337 cbrdlli_ast2150(ast, 16); /* 16 bits */ in ast_init_dram_reg()
339 cbrdlli_ast2150(ast, 32); /* 32 bits */ in ast_init_dram_reg()
342 switch (ast->chip) { in ast_init_dram_reg()
344 temp = ast_read32(ast, 0x10140); in ast_init_dram_reg()
345 ast_write32(ast, 0x10140, temp | 0x40); in ast_init_dram_reg()
351 temp = ast_read32(ast, 0x1200c); in ast_init_dram_reg()
352 ast_write32(ast, 0x1200c, temp & 0xfffffffd); in ast_init_dram_reg()
353 temp = ast_read32(ast, 0x12040); in ast_init_dram_reg()
354 ast_write32(ast, 0x12040, temp | 0x40); in ast_init_dram_reg()
363 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
369 struct ast_private *ast = to_ast_private(dev); in ast_post_gpu() local
378 ast_open_key(ast); in ast_post_gpu()
382 if (ast->chip == AST2600) { in ast_post_gpu()
384 } else if (ast->config_mode == ast_use_p2a) { in ast_post_gpu()
385 if (ast->chip == AST2500) in ast_post_gpu()
387 else if (ast->chip == AST2300 || ast->chip == AST2400) in ast_post_gpu()
394 if (ast->tx_chip_types & AST_TX_SIL164_BIT) in ast_post_gpu()
395 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
452 static bool mmc_test(struct ast_private *ast, u32 datagen, u8 test_ctl) in mmc_test() argument
456 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
457 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test()
460 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; in mmc_test()
464 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
468 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test()
472 static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl) in mmc_test2() argument
476 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
477 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test2()
480 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; in mmc_test2()
482 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test2()
486 data = ast_mindwm(ast, 0x1e6e0078); in mmc_test2()
488 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
493 static bool mmc_test_burst(struct ast_private *ast, u32 datagen) in mmc_test_burst() argument
495 return mmc_test(ast, datagen, 0xc1); in mmc_test_burst()
498 static u32 mmc_test_burst2(struct ast_private *ast, u32 datagen) in mmc_test_burst2() argument
500 return mmc_test2(ast, datagen, 0x41); in mmc_test_burst2()
503 static bool mmc_test_single(struct ast_private *ast, u32 datagen) in mmc_test_single() argument
505 return mmc_test(ast, datagen, 0xc5); in mmc_test_single()
508 static u32 mmc_test_single2(struct ast_private *ast, u32 datagen) in mmc_test_single2() argument
510 return mmc_test2(ast, datagen, 0x05); in mmc_test_single2()
513 static bool mmc_test_single_2500(struct ast_private *ast, u32 datagen) in mmc_test_single_2500() argument
515 return mmc_test(ast, datagen, 0x85); in mmc_test_single_2500()
518 static int cbr_test(struct ast_private *ast) in cbr_test() argument
522 data = mmc_test_single2(ast, 0); in cbr_test()
526 data = mmc_test_burst2(ast, i); in cbr_test()
537 static int cbr_scan(struct ast_private *ast) in cbr_scan() argument
543 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan()
545 if ((data = cbr_test(ast)) != 0) { in cbr_scan()
558 static u32 cbr_test2(struct ast_private *ast) in cbr_test2() argument
562 data = mmc_test_burst2(ast, 0); in cbr_test2()
565 data |= mmc_test_single2(ast, 0); in cbr_test2()
572 static u32 cbr_scan2(struct ast_private *ast) in cbr_scan2() argument
578 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan2()
580 if ((data = cbr_test2(ast)) != 0) { in cbr_scan2()
593 static bool cbr_test3(struct ast_private *ast) in cbr_test3() argument
595 if (!mmc_test_burst(ast, 0)) in cbr_test3()
597 if (!mmc_test_single(ast, 0)) in cbr_test3()
602 static bool cbr_scan3(struct ast_private *ast) in cbr_scan3() argument
607 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan3()
609 if (cbr_test3(ast)) in cbr_scan3()
618 static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param) in finetuneDQI_L() argument
629 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); in finetuneDQI_L()
630 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); in finetuneDQI_L()
631 data = cbr_scan2(ast); in finetuneDQI_L()
688 ast_moutdwm(ast, 0x1E6E0080, data); in finetuneDQI_L()
713 ast_moutdwm(ast, 0x1E6E0084, data); in finetuneDQI_L()
717 static void finetuneDQSI(struct ast_private *ast) in finetuneDQSI() argument
726 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); in finetuneDQSI()
727 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); in finetuneDQSI()
729 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
744 ast_moutdwm(ast, 0x1E6E000C, 0); in finetuneDQSI()
745 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); in finetuneDQSI()
746 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); in finetuneDQSI()
748 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in finetuneDQSI()
749 ast_moutdwm(ast, 0x1E6E0070, 0); in finetuneDQSI()
750 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); in finetuneDQSI()
751 if (cbr_scan3(ast)) { in finetuneDQSI()
804 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
807 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) in cbr_dll2() argument
812 finetuneDQSI(ast); in cbr_dll2()
813 if (finetuneDQI_L(ast, param) == false) in cbr_dll2()
821 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in cbr_dll2()
822 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); in cbr_dll2()
823 data = cbr_scan(ast); in cbr_dll2()
859 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); in cbr_dll2()
863 static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param) in get_ddr3_info() argument
867 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr3_info()
870 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr3_info()
884 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr3_info()
912 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr3_info()
942 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr3_info()
972 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr3_info()
986 ast_moutdwm(ast, 0x1E6E2020, 0x0270); in get_ddr3_info()
1000 ast_moutdwm(ast, 0x1E6E2020, 0x0290); in get_ddr3_info()
1016 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr3_info()
1034 ast_moutdwm(ast, 0x1E6E2020, 0x02E1); in get_ddr3_info()
1052 ast_moutdwm(ast, 0x1E6E2020, 0x0160); in get_ddr3_info()
1105 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param) in ddr3_init() argument
1110 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr3_init()
1111 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr3_init()
1112 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr3_init()
1113 ast_moutdwm(ast, 0x1E6E0034, 0x00000000); in ddr3_init()
1115 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr3_init()
1116 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr3_init()
1118 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr3_init()
1121 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr3_init()
1122 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr3_init()
1123 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr3_init()
1124 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr3_init()
1125 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr3_init()
1126 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr3_init()
1127 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr3_init()
1128 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr3_init()
1129 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); in ddr3_init()
1130 ast_moutdwm(ast, 0x1E6E0018, 0x00002370); in ddr3_init()
1131 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr3_init()
1132 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); in ddr3_init()
1133 ast_moutdwm(ast, 0x1E6E0044, 0x22222222); in ddr3_init()
1134 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr3_init()
1135 ast_moutdwm(ast, 0x1E6E004C, 0x00000002); in ddr3_init()
1136 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1137 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1138 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr3_init()
1139 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr3_init()
1140 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr3_init()
1141 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1142 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr3_init()
1143 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr3_init()
1144 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1147 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1149 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1152 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr3_init()
1156 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr3_init()
1162 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr3_init()
1165 ast_moutdwm(ast, 0x1E6E0068, data); in ddr3_init()
1167 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr3_init()
1169 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr3_init()
1170 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1172 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1174 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1177 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1180 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); in ddr3_init()
1181 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr3_init()
1182 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1184 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr3_init()
1185 ast_moutdwm(ast, 0x1E6E000C, 0x00000040); in ddr3_init()
1188 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr3_init()
1189 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr3_init()
1190 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr3_init()
1191 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr3_init()
1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr3_init()
1193 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1194 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr3_init()
1195 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr3_init()
1196 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1198 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr3_init()
1206 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr3_init()
1209 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr3_init()
1212 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr3_init()
1215 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1216 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr3_init()
1218 data = ast_mindwm(ast, 0x1E6E0070); in ddr3_init()
1220 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1221 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1222 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1228 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param) in get_ddr2_info() argument
1232 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr2_info()
1235 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr2_info()
1249 ast_moutdwm(ast, 0x1E6E2020, 0x0130); in get_ddr2_info()
1264 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr2_info()
1295 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr2_info()
1329 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr2_info()
1362 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr2_info()
1377 ast_moutdwm(ast, 0x1E6E2020, 0x0261); in get_ddr2_info()
1393 ast_moutdwm(ast, 0x1E6E2020, 0x0120); in get_ddr2_info()
1409 ast_moutdwm(ast, 0x1E6E2020, 0x02A1); in get_ddr2_info()
1425 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr2_info()
1475 static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param) in ddr2_init() argument
1480 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr2_init()
1481 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr2_init()
1482 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr2_init()
1483 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr2_init()
1484 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr2_init()
1486 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr2_init()
1489 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr2_init()
1490 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr2_init()
1491 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr2_init()
1492 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr2_init()
1493 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr2_init()
1494 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr2_init()
1495 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr2_init()
1496 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr2_init()
1497 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); in ddr2_init()
1498 ast_moutdwm(ast, 0x1E6E0018, 0x00002330); in ddr2_init()
1499 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr2_init()
1500 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); in ddr2_init()
1501 ast_moutdwm(ast, 0x1E6E0044, 0x88848466); in ddr2_init()
1502 ast_moutdwm(ast, 0x1E6E0048, 0x44440008); in ddr2_init()
1503 ast_moutdwm(ast, 0x1E6E004C, 0x00000000); in ddr2_init()
1504 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1505 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1506 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr2_init()
1507 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr2_init()
1508 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr2_init()
1509 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1510 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr2_init()
1511 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr2_init()
1512 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1516 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1518 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1521 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr2_init()
1525 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr2_init()
1531 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr2_init()
1534 ast_moutdwm(ast, 0x1E6E0068, data); in ddr2_init()
1536 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr2_init()
1538 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr2_init()
1539 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1541 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1543 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1546 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1549 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); in ddr2_init()
1550 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr2_init()
1551 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1553 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr2_init()
1554 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr2_init()
1557 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr2_init()
1558 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1559 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr2_init()
1560 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr2_init()
1561 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1562 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1564 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr2_init()
1565 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr2_init()
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1567 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); in ddr2_init()
1568 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1569 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1570 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1572 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); in ddr2_init()
1580 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr2_init()
1581 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr2_init()
1584 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) in ddr2_init()
1589 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1590 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr2_init()
1592 data = ast_mindwm(ast, 0x1E6E0070); in ddr2_init()
1594 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1595 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1596 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1603 struct ast_private *ast = to_ast_private(dev); in ast_post_chip_2300() local
1608 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1610 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_post_chip_2300()
1611 ast_write32(ast, 0xf000, 0x1); in ast_post_chip_2300()
1612 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_post_chip_2300()
1615 } while (ast_read32(ast, 0x12000) != 0x1); in ast_post_chip_2300()
1617 ast_write32(ast, 0x10000, 0xfc600309); in ast_post_chip_2300()
1620 } while (ast_read32(ast, 0x10000) != 0x1); in ast_post_chip_2300()
1623 temp = ast_read32(ast, 0x12008); in ast_post_chip_2300()
1625 ast_write32(ast, 0x12008, temp); in ast_post_chip_2300()
1629 temp = ast_mindwm(ast, 0x1e6e2070); in ast_post_chip_2300()
1667 get_ddr3_info(ast, ¶m); in ast_post_chip_2300()
1668 ddr3_init(ast, ¶m); in ast_post_chip_2300()
1670 get_ddr2_info(ast, ¶m); in ast_post_chip_2300()
1671 ddr2_init(ast, ¶m); in ast_post_chip_2300()
1674 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2300()
1675 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2300()
1680 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1684 static bool cbr_test_2500(struct ast_private *ast) in cbr_test_2500() argument
1686 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in cbr_test_2500()
1687 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in cbr_test_2500()
1688 if (!mmc_test_burst(ast, 0)) in cbr_test_2500()
1690 if (!mmc_test_single_2500(ast, 0)) in cbr_test_2500()
1695 static bool ddr_test_2500(struct ast_private *ast) in ddr_test_2500() argument
1697 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in ddr_test_2500()
1698 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in ddr_test_2500()
1699 if (!mmc_test_burst(ast, 0)) in ddr_test_2500()
1701 if (!mmc_test_burst(ast, 1)) in ddr_test_2500()
1703 if (!mmc_test_burst(ast, 2)) in ddr_test_2500()
1705 if (!mmc_test_burst(ast, 3)) in ddr_test_2500()
1707 if (!mmc_test_single_2500(ast, 0)) in ddr_test_2500()
1712 static void ddr_init_common_2500(struct ast_private *ast) in ddr_init_common_2500() argument
1714 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in ddr_init_common_2500()
1715 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); in ddr_init_common_2500()
1716 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); in ddr_init_common_2500()
1717 ast_moutdwm(ast, 0x1E6E0040, 0x88448844); in ddr_init_common_2500()
1718 ast_moutdwm(ast, 0x1E6E0044, 0x24422288); in ddr_init_common_2500()
1719 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr_init_common_2500()
1720 ast_moutdwm(ast, 0x1E6E004C, 0x22222222); in ddr_init_common_2500()
1721 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr_init_common_2500()
1722 ast_moutdwm(ast, 0x1E6E0208, 0x00000000); in ddr_init_common_2500()
1723 ast_moutdwm(ast, 0x1E6E0218, 0x00000000); in ddr_init_common_2500()
1724 ast_moutdwm(ast, 0x1E6E0220, 0x00000000); in ddr_init_common_2500()
1725 ast_moutdwm(ast, 0x1E6E0228, 0x00000000); in ddr_init_common_2500()
1726 ast_moutdwm(ast, 0x1E6E0230, 0x00000000); in ddr_init_common_2500()
1727 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); in ddr_init_common_2500()
1728 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); in ddr_init_common_2500()
1729 ast_moutdwm(ast, 0x1E6E0240, 0x86000000); in ddr_init_common_2500()
1730 ast_moutdwm(ast, 0x1E6E0244, 0x00008600); in ddr_init_common_2500()
1731 ast_moutdwm(ast, 0x1E6E0248, 0x80000000); in ddr_init_common_2500()
1732 ast_moutdwm(ast, 0x1E6E024C, 0x80808080); in ddr_init_common_2500()
1735 static void ddr_phy_init_2500(struct ast_private *ast) in ddr_phy_init_2500() argument
1740 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1743 data = ast_mindwm(ast, 0x1E6E0060) & 0x1; in ddr_phy_init_2500()
1748 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; in ddr_phy_init_2500()
1753 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr_phy_init_2500()
1755 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1759 ast_moutdwm(ast, 0x1E6E0060, 0x00000006); in ddr_phy_init_2500()
1769 static void check_dram_size_2500(struct ast_private *ast, u32 tRFC) in check_dram_size_2500() argument
1773 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; in check_dram_size_2500()
1774 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; in check_dram_size_2500()
1776 ast_moutdwm(ast, 0xA0100000, 0x41424344); in check_dram_size_2500()
1777 ast_moutdwm(ast, 0x90100000, 0x35363738); in check_dram_size_2500()
1778 ast_moutdwm(ast, 0x88100000, 0x292A2B2C); in check_dram_size_2500()
1779 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); in check_dram_size_2500()
1782 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { in check_dram_size_2500()
1786 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { in check_dram_size_2500()
1790 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { in check_dram_size_2500()
1796 ast_moutdwm(ast, 0x1E6E0004, reg_04); in check_dram_size_2500()
1797 ast_moutdwm(ast, 0x1E6E0014, reg_14); in check_dram_size_2500()
1800 static void enable_cache_2500(struct ast_private *ast) in enable_cache_2500() argument
1804 reg_04 = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1805 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); in enable_cache_2500()
1808 data = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1810 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); in enable_cache_2500()
1813 static void set_mpll_2500(struct ast_private *ast) in set_mpll_2500() argument
1818 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in set_mpll_2500()
1819 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in set_mpll_2500()
1821 ast_moutdwm(ast, addr, 0x0); in set_mpll_2500()
1824 ast_moutdwm(ast, 0x1E6E0034, 0x00020000); in set_mpll_2500()
1826 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in set_mpll_2500()
1827 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; in set_mpll_2500()
1831 ast_moutdwm(ast, 0x1E6E2160, 0x00011320); in set_mpll_2500()
1836 ast_moutdwm(ast, 0x1E6E2020, param); in set_mpll_2500()
1840 static void reset_mmc_2500(struct ast_private *ast) in reset_mmc_2500() argument
1842 ast_moutdwm(ast, 0x1E78505C, 0x00000004); in reset_mmc_2500()
1843 ast_moutdwm(ast, 0x1E785044, 0x00000001); in reset_mmc_2500()
1844 ast_moutdwm(ast, 0x1E785048, 0x00004755); in reset_mmc_2500()
1845 ast_moutdwm(ast, 0x1E78504C, 0x00000013); in reset_mmc_2500()
1847 ast_moutdwm(ast, 0x1E785054, 0x00000077); in reset_mmc_2500()
1848 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in reset_mmc_2500()
1851 static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table) in ddr3_init_2500() argument
1854 ast_moutdwm(ast, 0x1E6E0004, 0x00000303); in ddr3_init_2500()
1855 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr3_init_2500()
1856 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr3_init_2500()
1857 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr3_init_2500()
1858 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr3_init_2500()
1859 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr3_init_2500()
1860 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr3_init_2500()
1861 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr3_init_2500()
1864 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); in ddr3_init_2500()
1865 ast_moutdwm(ast, 0x1E6E0204, 0x00001001); in ddr3_init_2500()
1866 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr3_init_2500()
1867 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr3_init_2500()
1868 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr3_init_2500()
1869 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr3_init_2500()
1870 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr3_init_2500()
1871 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr3_init_2500()
1872 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr3_init_2500()
1873 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr3_init_2500()
1874 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr3_init_2500()
1875 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr3_init_2500()
1876 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr3_init_2500()
1877 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); in ddr3_init_2500()
1880 ast_moutdwm(ast, 0x1E6E0034, 0x00020091); in ddr3_init_2500()
1883 ddr_phy_init_2500(ast); in ddr3_init_2500()
1885 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr3_init_2500()
1886 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr3_init_2500()
1887 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr3_init_2500()
1889 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr3_init_2500()
1890 enable_cache_2500(ast); in ddr3_init_2500()
1891 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr3_init_2500()
1892 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr3_init_2500()
1895 static void ddr4_init_2500(struct ast_private *ast, const u32 *ddr_table) in ddr4_init_2500() argument
1902 ast_moutdwm(ast, 0x1E6E0004, 0x00000313); in ddr4_init_2500()
1903 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr4_init_2500()
1904 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr4_init_2500()
1905 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr4_init_2500()
1906 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr4_init_2500()
1907 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr4_init_2500()
1908 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr4_init_2500()
1909 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr4_init_2500()
1912 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); in ddr4_init_2500()
1913 ast_moutdwm(ast, 0x1E6E0204, 0x09002000); in ddr4_init_2500()
1914 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr4_init_2500()
1915 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr4_init_2500()
1916 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr4_init_2500()
1917 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr4_init_2500()
1918 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr4_init_2500()
1919 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr4_init_2500()
1920 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr4_init_2500()
1921 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr4_init_2500()
1922 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr4_init_2500()
1923 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr4_init_2500()
1924 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr4_init_2500()
1925 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); in ddr4_init_2500()
1926 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); in ddr4_init_2500()
1929 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); in ddr4_init_2500()
1937 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); in ddr4_init_2500()
1939 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1940 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1941 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); in ddr4_init_2500()
1943 ddr_phy_init_2500(ast); in ddr4_init_2500()
1944 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1945 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1947 data = ast_mindwm(ast, 0x1E6E03D0); in ddr4_init_2500()
1960 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); in ddr4_init_2500()
1970 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1971 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1972 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1974 ddr_phy_init_2500(ast); in ddr4_init_2500()
1975 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1976 if (cbr_test_2500(ast)) { in ddr4_init_2500()
1987 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1988 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1990 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1993 ddr_phy_init_2500(ast); in ddr4_init_2500()
1995 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr4_init_2500()
1996 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr4_init_2500()
1997 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr4_init_2500()
1999 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]); in ddr4_init_2500()
2000 enable_cache_2500(ast); in ddr4_init_2500()
2001 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr4_init_2500()
2002 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr4_init_2500()
2005 static bool ast_dram_init_2500(struct ast_private *ast) in ast_dram_init_2500() argument
2013 set_mpll_2500(ast); in ast_dram_init_2500()
2014 reset_mmc_2500(ast); in ast_dram_init_2500()
2015 ddr_init_common_2500(ast); in ast_dram_init_2500()
2017 data = ast_mindwm(ast, 0x1E6E2070); in ast_dram_init_2500()
2019 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table); in ast_dram_init_2500()
2021 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table); in ast_dram_init_2500()
2022 } while (!ddr_test_2500(ast)); in ast_dram_init_2500()
2024 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); in ast_dram_init_2500()
2027 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; in ast_dram_init_2500()
2028 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); in ast_dram_init_2500()
2033 void ast_patch_ahb_2500(struct ast_private *ast) in ast_patch_ahb_2500() argument
2038 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); in ast_patch_ahb_2500()
2039 ast_moutdwm(ast, 0x1e600084, 0x00010000); in ast_patch_ahb_2500()
2040 ast_moutdwm(ast, 0x1e600088, 0x00000000); in ast_patch_ahb_2500()
2041 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); in ast_patch_ahb_2500()
2042 data = ast_mindwm(ast, 0x1e6e2070); in ast_patch_ahb_2500()
2055 ast_moutdwm(ast, 0x1E785004, 0x00000010); in ast_patch_ahb_2500()
2056 ast_moutdwm(ast, 0x1E785008, 0x00004755); in ast_patch_ahb_2500()
2057 ast_moutdwm(ast, 0x1E78500c, 0x00000033); in ast_patch_ahb_2500()
2061 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); in ast_patch_ahb_2500()
2062 data = ast_mindwm(ast, 0x1e6e2000); in ast_patch_ahb_2500()
2064 ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ in ast_patch_ahb_2500()
2069 struct ast_private *ast = to_ast_private(dev); in ast_post_chip_2500() local
2073 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()
2076 ast_patch_ahb_2500(ast); in ast_post_chip_2500()
2079 ast_moutdwm(ast, 0x1E78502C, 0x00000000); in ast_post_chip_2500()
2080 ast_moutdwm(ast, 0x1E78504C, 0x00000000); in ast_post_chip_2500()
2095 ast_moutdwm(ast, 0x1E6E2090, 0x20000000); in ast_post_chip_2500()
2096 ast_moutdwm(ast, 0x1E6E2094, 0x00004000); in ast_post_chip_2500()
2097 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { in ast_post_chip_2500()
2098 ast_moutdwm(ast, 0x1E6E207C, 0x00800000); in ast_post_chip_2500()
2100 ast_moutdwm(ast, 0x1E6E2070, 0x00800000); in ast_post_chip_2500()
2103 temp = ast_mindwm(ast, 0x1E6E2070); in ast_post_chip_2500()
2105 ast_moutdwm(ast, 0x1E6E207C, 0x00004000); in ast_post_chip_2500()
2108 temp = ast_read32(ast, 0x12008); in ast_post_chip_2500()
2110 ast_write32(ast, 0x12008, temp); in ast_post_chip_2500()
2112 if (!ast_dram_init_2500(ast)) in ast_post_chip_2500()
2115 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2500()
2116 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2500()
2121 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()