37 		((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
41 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_sclk()
48 	ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle,  in amdgpu_dpm_get_sclk()
57 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_mclk()
64 	ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle,  in amdgpu_dpm_get_mclk()
74 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_powergating_by_smu()
96 				(adev)->powerplay.pp_handle, block_type, gate));  in amdgpu_dpm_set_powergating_by_smu()
112 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_set_gfx_power_up_by_imu()
126 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_baco_enter()
127 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_baco_enter()
145 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_baco_exit()
146 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_baco_exit()
166 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_mp1_state()
172 				adev->powerplay.pp_handle,  in amdgpu_dpm_set_mp1_state()
183 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_is_baco_supported()
184 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_is_baco_supported()
214 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_mode2_reset()
215 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_mode2_reset()
232 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_baco_reset()
233 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_baco_reset()
256 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_is_mode1_reset_supported()
270 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_mode1_reset()
286 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_switch_power_profile()
295 			adev->powerplay.pp_handle, type, en);  in amdgpu_dpm_switch_power_profile()
305 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_xgmi_pstate()
310 		ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,  in amdgpu_dpm_set_xgmi_pstate()
322 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_df_cstate()
323 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_set_df_cstate()
336 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_allow_xgmi_power_down()
350 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_enable_mgpu_fan_boost()
352 			adev->powerplay.pp_funcs;  in amdgpu_dpm_enable_mgpu_fan_boost()
367 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_set_clockgating_by_smu()
369 			adev->powerplay.pp_funcs;  in amdgpu_dpm_set_clockgating_by_smu()
385 	void *pp_handle = adev->powerplay.pp_handle;  in amdgpu_dpm_smu_i2c_bus_access()
387 			adev->powerplay.pp_funcs;  in amdgpu_dpm_smu_i2c_bus_access()
409 		if (adev->powerplay.pp_funcs &&  in amdgpu_pm_acpi_event_handler()
410 		    adev->powerplay.pp_funcs->enable_bapm)  in amdgpu_pm_acpi_event_handler()
414 			smu_set_ac_dc(adev->powerplay.pp_handle);  in amdgpu_pm_acpi_event_handler()
423 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_read_sensor()
431 		ret = pp_funcs->read_sensor(adev->powerplay.pp_handle,  in amdgpu_dpm_read_sensor()
443 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_compute_clocks()
462 	pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle);  in amdgpu_dpm_compute_clocks()
527 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_pm_load_smu_firmware()
534 	r = pp_funcs->load_firmware(adev->powerplay.pp_handle);  in amdgpu_pm_load_smu_firmware()
554 		ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle,  in amdgpu_dpm_handle_passthrough_sbr()
564 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_send_hbm_bad_pages_num()
579 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_send_hbm_bad_channel_flag()
606 	ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle,  in amdgpu_dpm_get_dpm_freq_range()
620 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_set_soft_freq_range()
641 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_write_watermarks_table()
658 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_wait_for_event()
673 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_set_residency_gfxoff()
688 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_residency_gfxoff()
703 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_entrycount_gfxoff()
718 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_status_gfxoff()
733 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_thermal_throttling_counter()
750 	if (adev->powerplay.pp_funcs &&  in amdgpu_dpm_gfx_state_change()
751 	    adev->powerplay.pp_funcs->gfx_state_change_set)  in amdgpu_dpm_gfx_state_change()
752 		((adev)->powerplay.pp_funcs->gfx_state_change_set(  in amdgpu_dpm_gfx_state_change()
753 			(adev)->powerplay.pp_handle, state));  in amdgpu_dpm_gfx_state_change()
760 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_ecc_info()
776 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_vce_clock_state()
783 	vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle,  in amdgpu_dpm_get_vce_clock_state()
793 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_current_power_state()
802 	*state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle);  in amdgpu_dpm_get_current_power_state()
829 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_performance_level()
837 		level = pp_funcs->get_performance_level(adev->powerplay.pp_handle);  in amdgpu_dpm_get_performance_level()
848 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_force_performance_level()
902 	if (pp_funcs->force_performance_level(adev->powerplay.pp_handle,  in amdgpu_dpm_force_performance_level()
918 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_pp_num_states()
925 	ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle,  in amdgpu_dpm_get_pp_num_states()
936 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_dispatch_task()
943 	ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle,  in amdgpu_dpm_dispatch_task()
953 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_pp_table()
960 	ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle,  in amdgpu_dpm_get_pp_table()
972 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fine_grain_clk_vol()
979 	ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fine_grain_clk_vol()
993 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_odn_edit_dpm_table()
1000 	ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle,  in amdgpu_dpm_odn_edit_dpm_table()
1013 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_print_clock_levels()
1020 	ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle,  in amdgpu_dpm_print_clock_levels()
1033 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_emit_clock_levels()
1040 	ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle,  in amdgpu_dpm_emit_clock_levels()
1052 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_ppfeature_status()
1059 	ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle,  in amdgpu_dpm_set_ppfeature_status()
1068 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_ppfeature_status()
1075 	ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle,  in amdgpu_dpm_get_ppfeature_status()
1086 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_force_clock_level()
1093 	ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle,  in amdgpu_dpm_force_clock_level()
1103 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_sclk_od()
1110 	ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle);  in amdgpu_dpm_get_sclk_od()
1118 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_sclk_od()
1125 		pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value);  in amdgpu_dpm_set_sclk_od()
1140 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_mclk_od()
1147 	ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle);  in amdgpu_dpm_get_mclk_od()
1155 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_mclk_od()
1162 		pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value);  in amdgpu_dpm_set_mclk_od()
1178 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_power_profile_mode()
1185 	ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_get_power_profile_mode()
1195 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_power_profile_mode()
1202 	ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_set_power_profile_mode()
1212 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_gpu_metrics()
1219 	ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle,  in amdgpu_dpm_get_gpu_metrics()
1229 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_fan_control_mode()
1236 	ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_get_fan_control_mode()
1246 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fan_speed_pwm()
1253 	ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fan_speed_pwm()
1263 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_fan_speed_pwm()
1270 	ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle,  in amdgpu_dpm_get_fan_speed_pwm()
1280 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_fan_speed_rpm()
1287 	ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle,  in amdgpu_dpm_get_fan_speed_rpm()
1297 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fan_speed_rpm()
1304 	ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fan_speed_rpm()
1314 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_fan_control_mode()
1321 	ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle,  in amdgpu_dpm_set_fan_control_mode()
1333 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_power_limit()
1340 	ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle,  in amdgpu_dpm_get_power_limit()
1352 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_power_limit()
1359 	ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle,  in amdgpu_dpm_set_power_limit()
1383 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_debugfs_print_current_performance_level()
1389 	pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle,  in amdgpu_dpm_debugfs_print_current_performance_level()
1400 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_smu_prv_buf_details()
1407 	ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle,  in amdgpu_dpm_get_smu_prv_buf_details()
1417 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;  in amdgpu_dpm_is_overdrive_supported()
1418 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_is_overdrive_supported()
1432 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_pp_table()
1439 	ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle,  in amdgpu_dpm_set_pp_table()
1449 	struct smu_context *smu = adev->powerplay.pp_handle;  in amdgpu_dpm_get_num_cpu_cores()
1468 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_display_configuration_change()
1475 	ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle,  in amdgpu_dpm_display_configuration_change()
1486 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_clock_by_type()
1493 	ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle,  in amdgpu_dpm_get_clock_by_type()
1504 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_display_mode_validation_clks()
1511 	ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle,  in amdgpu_dpm_get_display_mode_validation_clks()
1522 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_clock_by_type_with_latency()
1529 	ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle,  in amdgpu_dpm_get_clock_by_type_with_latency()
1541 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_clock_by_type_with_voltage()
1548 	ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle,  in amdgpu_dpm_get_clock_by_type_with_voltage()
1559 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1566 	ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle,  in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1576 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_display_clock_voltage_request()
1583 	ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle,  in amdgpu_dpm_display_clock_voltage_request()
1593 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_current_clocks()
1600 	ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle,  in amdgpu_dpm_get_current_clocks()
1609 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_notify_smu_enable_pwe()
1615 	pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle);  in amdgpu_dpm_notify_smu_enable_pwe()
1622 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_active_display_count()
1629 	ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle,  in amdgpu_dpm_set_active_display_count()
1639 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1646 	ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle,  in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1656 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1662 	pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle,  in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1670 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_set_hard_min_fclk_by_freq()
1676 	pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle,  in amdgpu_dpm_set_hard_min_fclk_by_freq()
1684 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_display_disable_memory_clock_switch()
1691 	ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle,  in amdgpu_dpm_display_disable_memory_clock_switch()
1701 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1708 	ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle,  in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1719 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_uclk_dpm_states()
1726 	ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle,  in amdgpu_dpm_get_uclk_dpm_states()
1737 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;  in amdgpu_dpm_get_dpm_clock_table()
1744 	ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle,  in amdgpu_dpm_get_dpm_clock_table()