Lines Matching refs:SR
160 #define SR(reg_name)\ macro
673 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
674 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
675 SR(DIO_MEM_PWR_CTRL), \
676 SR(ODM_MEM_PWR_CTRL3), \
677 SR(DMU_MEM_PWR_CNTL), \
678 SR(MMHUBBUB_MEM_PWR_CNTL), \
679 SR(DCCG_GATE_DISABLE_CNTL), \
680 SR(DCCG_GATE_DISABLE_CNTL2), \
681 SR(DCFCLK_CNTL),\
682 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
691 SR(MICROSECOND_TIME_BASE_DIV), \
692 SR(MILLISECOND_TIME_BASE_DIV), \
693 SR(DISPCLK_FREQ_CHANGE_CNTL), \
694 SR(RBBMIF_TIMEOUT_DIS), \
695 SR(RBBMIF_TIMEOUT_DIS_2), \
696 SR(DCHUBBUB_CRC_CTRL), \
697 SR(DPP_TOP0_DPP_CRC_CTRL), \
698 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
699 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
700 SR(MPC_CRC_CTRL), \
701 SR(MPC_CRC_RESULT_GB), \
702 SR(MPC_CRC_RESULT_C), \
703 SR(MPC_CRC_RESULT_AR), \
704 SR(DOMAIN0_PG_CONFIG), \
705 SR(DOMAIN1_PG_CONFIG), \
706 SR(DOMAIN2_PG_CONFIG), \
707 SR(DOMAIN3_PG_CONFIG), \
708 SR(DOMAIN16_PG_CONFIG), \
709 SR(DOMAIN17_PG_CONFIG), \
710 SR(DOMAIN18_PG_CONFIG), \
711 SR(DOMAIN0_PG_STATUS), \
712 SR(DOMAIN1_PG_STATUS), \
713 SR(DOMAIN2_PG_STATUS), \
714 SR(DOMAIN3_PG_STATUS), \
715 SR(DOMAIN16_PG_STATUS), \
716 SR(DOMAIN17_PG_STATUS), \
717 SR(DOMAIN18_PG_STATUS), \
718 SR(D1VGA_CONTROL), \
719 SR(D2VGA_CONTROL), \
720 SR(D3VGA_CONTROL), \
721 SR(D4VGA_CONTROL), \
722 SR(D5VGA_CONTROL), \
723 SR(D6VGA_CONTROL), \
724 SR(DC_IP_REQUEST_CNTL), \
725 SR(AZALIA_AUDIO_DTO), \
726 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
727 SR(HPO_TOP_HW_CONTROL)