Lines Matching refs:SR
159 #define SR(reg_name)\ macro
697 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
698 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
699 SR(DIO_MEM_PWR_CTRL), \
700 SR(ODM_MEM_PWR_CTRL3), \
701 SR(DMU_MEM_PWR_CNTL), \
702 SR(MMHUBBUB_MEM_PWR_CNTL), \
703 SR(DCCG_GATE_DISABLE_CNTL), \
704 SR(DCCG_GATE_DISABLE_CNTL2), \
705 SR(DCFCLK_CNTL),\
706 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
715 SR(MICROSECOND_TIME_BASE_DIV), \
716 SR(MILLISECOND_TIME_BASE_DIV), \
717 SR(DISPCLK_FREQ_CHANGE_CNTL), \
718 SR(RBBMIF_TIMEOUT_DIS), \
719 SR(RBBMIF_TIMEOUT_DIS_2), \
720 SR(DCHUBBUB_CRC_CTRL), \
721 SR(DPP_TOP0_DPP_CRC_CTRL), \
722 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
723 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
724 SR(MPC_CRC_CTRL), \
725 SR(MPC_CRC_RESULT_GB), \
726 SR(MPC_CRC_RESULT_C), \
727 SR(MPC_CRC_RESULT_AR), \
728 SR(DOMAIN0_PG_CONFIG), \
729 SR(DOMAIN1_PG_CONFIG), \
730 SR(DOMAIN2_PG_CONFIG), \
731 SR(DOMAIN3_PG_CONFIG), \
732 SR(DOMAIN16_PG_CONFIG), \
733 SR(DOMAIN17_PG_CONFIG), \
734 SR(DOMAIN18_PG_CONFIG), \
735 SR(DOMAIN19_PG_CONFIG), \
736 SR(DOMAIN0_PG_STATUS), \
737 SR(DOMAIN1_PG_STATUS), \
738 SR(DOMAIN2_PG_STATUS), \
739 SR(DOMAIN3_PG_STATUS), \
740 SR(DOMAIN16_PG_STATUS), \
741 SR(DOMAIN17_PG_STATUS), \
742 SR(DOMAIN18_PG_STATUS), \
743 SR(DOMAIN19_PG_STATUS), \
744 SR(D1VGA_CONTROL), \
745 SR(D2VGA_CONTROL), \
746 SR(D3VGA_CONTROL), \
747 SR(D4VGA_CONTROL), \
748 SR(D5VGA_CONTROL), \
749 SR(D6VGA_CONTROL), \
750 SR(DC_IP_REQUEST_CNTL), \
751 SR(AZALIA_AUDIO_DTO), \
752 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
753 SR(HPO_TOP_HW_CONTROL)