Lines Matching refs:SR
32 SR(DPPCLK_DTO_CTRL),\
37 SR(PHYASYMCLK_CLOCK_CNTL),\
38 SR(PHYBSYMCLK_CLOCK_CNTL),\
39 SR(PHYCSYMCLK_CLOCK_CNTL),\
40 SR(PHYDSYMCLK_CLOCK_CNTL),\
41 SR(PHYESYMCLK_CLOCK_CNTL),\
42 SR(DPSTREAMCLK_CNTL),\
43 SR(SYMCLK32_SE_CNTL),\
44 SR(SYMCLK32_LE_CNTL),\
57 SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
58 SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
59 SR(DCCG_AUDIO_DTO_SOURCE),\
60 SR(DENTIST_DISPCLK_CNTL),\
61 SR(DSCCLK0_DTO_PARAM),\
62 SR(DSCCLK1_DTO_PARAM),\
63 SR(DSCCLK2_DTO_PARAM),\
64 SR(DSCCLK_DTO_CTRL),\
65 SR(DCCG_GATE_DISABLE_CNTL2),\
66 SR(DCCG_GATE_DISABLE_CNTL3),\
67 SR(HDMISTREAMCLK0_DTO_PARAM)